| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
|
| /external/openssl/crypto/sha/asm/ |
| sha512-mips.pl | 84 $SRL="dsrl"; # shift right logical
98 $SRL="srl"; # shift right logical
127 srl $tmp0,@X[0],24 # byte swap($i)
128 srl $tmp1,@X[0],8
159 $SRL $h,$e,@Sigma1[0]
163 $SRL $tmp0,$e,@Sigma1[1]
167 $SRL $tmp0,$e,@Sigma1[2]
174 $SRL $h,$a,@Sigma0[0]
179 $SRL $tmp0,$a,@Sigma0[1
[all...] |
| sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical
85 $SRL="srl"; # shift right logical
222 $SRL $e,@Sigma1[0],$h !! $i
226 $SRL $e,@Sigma1[1],$tmp0
230 $SRL $e,@Sigma1[2],$tmp0
237 $SRL $a,@Sigma0[0],$h
242 $SRL $a,@Sigma0[1],$tmp0
246 $SRL $a,@Sigma0[2],$tmp0
276 srl $xi,@sigma0[0],$T1 !! Xupdate($i
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 209 { ISD::SRL, MVT::v4i32, 1 },
212 { ISD::SRL, MVT::v8i32, 1 },
215 { ISD::SRL, MVT::v2i64, 1 },
217 { ISD::SRL, MVT::v4i64, 1 },
222 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
223 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
264 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
265 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
266 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
267 { ISD::SRL, MVT::v2i64, 1 }, // psrlq
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 184 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
|
| SystemZInstrInfo.cpp | 454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
455 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
476 eraseIfDead(SRL, MRI);
[all...] |
| /external/chromium_org/v8/src/mips/ |
| constants-mips.cc | 225 case SRL:
|
| /external/chromium_org/v8/src/mips64/ |
| constants-mips64.cc | 227 case SRL:
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memcpy.S | 111 #define SRL dsrl
147 #define SRL srl
238 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
360 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 614 if (InOp.getOpcode() == ISD::SRL &&
622 Opc = ISD::SRL;
662 InnerOp.getOpcode() == ISD::SRL &&
689 case ISD::SRL:
707 unsigned Opc = ISD::SRL;
740 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
[all...] |
| LegalizeIntegerTypes.cpp | 77 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
299 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
608 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
707 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
[all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeDAG.cpp | 406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
[all...] |
| LegalizeVectorOps.cpp | 75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
255 case ISD::SRL:
519 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 94 setOperationAction(ISD::SRL, MVT::i8, Custom);
97 setOperationAction(ISD::SRL, MVT::i16, Custom);
188 case ISD::SRL:
755 case ISD::SRL:
756 return DAG.getNode(MSP430ISD::SRL, dl,
767 if (Opc == ISD::SRL && ShiftAmount) {
769 // srl A, 1 => clrc; rrc A
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeSPARC_32.c | 71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
|
| sljitNativeMIPS_32.c | 135 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG));
271 return push_inst(compiler, SRL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
332 EMIT_SHIFT(SRL, SRLV);
|
| sljitNativeMIPS_64.c | 227 FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG));
363 return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV);
|
| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.c | 10 SRA, SRAV, SRL, SRLV
189 case SRL:
190 TEST2("srl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
191 TEST2("srl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
192 TEST2("srl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
193 TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 390 } else if (Opcode == ISD::SRL) {
437 Op0.getOperand(0).getOpcode() == ISD::SRL) {
439 Op1.getOperand(0).getOpcode() != ISD::SRL) {
445 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
447 Op1.getOperand(0).getOpcode() != ISD::SRL) {
458 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
472 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
[all...] |
| /external/openssl/crypto/bn/asm/ |
| mips.pl | 62 $SRL="dsrl";
77 $SRL="srl";
899 $SRL $at,$a1,$t1
914 $SRL $DH,$a2,4*$BNSZ # bits
923 $SRL $HH,$a0,4*$BNSZ # bits
924 $SRL $QT,4*$BNSZ # q=0xffffffff
931 $SRL $at,$a1,4*$BNSZ # bits
956 $SRL $HH,$a0,4*$BNSZ # bits
957 $SRL $QT,4*$BNSZ # q=0xfffffff
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | [all...] |
