/external/llvm/include/llvm/Target/ |
TargetOpcodes.h | 54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that 58 SUBREG_TO_REG = 9,
|
/external/llvm/lib/CodeGen/ |
ExpandPostRAPseudos.cpp | 10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo 84 MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); 110 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3 210 case TargetOpcode::SUBREG_TO_REG:
|
PeepholeOptimizer.cpp | 323 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 330 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 332 // The problem here is that SUBREG_TO_REG is there to assert that an 336 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 715 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 756 case TargetOpcode::SUBREG_TO_REG: [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ResourcePriorityQueue.cpp | 267 case TargetOpcode::SUBREG_TO_REG: 307 case TargetOpcode::SUBREG_TO_REG:
|
InstrEmitter.cpp | 522 Opc == TargetOpcode::SUBREG_TO_REG) { 549 // Create the insert_subreg or subreg_to_reg machine instruction. 553 // If creating a subreg_to_reg, then the first input operand 555 if (Opc == TargetOpcode::SUBREG_TO_REG) { 567 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 715 Opc == TargetOpcode::SUBREG_TO_REG) { [all...] |
ScheduleDAGRRList.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 55 case TargetOpcode::SUBREG_TO_REG: 107 case TargetOpcode::SUBREG_TO_REG:
|
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | [all...] |
AArch64ISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | [all...] |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelDAGToDAG.cpp | [all...] |
X86FastISel.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | [all...] |