| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 48 SXTX,
67 case AArch64_AM::SXTX: return "sxtx";
134 case 7: return AArch64_AM::SXTX;
150 /// 111 ==> sxtx
161 case AArch64_AM::SXTX: return 7; break;
197 /// 111 ==> sxtx
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | 386 COMPARE(adds(cp, jssp, Operand(fp, SXTX)), "adds cp, jssp, fp, sxtx");
412 COMPARE(subs(cp, jssp, Operand(fp, SXTX)), "subs cp, jssp, fp, sxtx");
[all...] |
| test-assembler-arm64.cc | 569 __ Orr(x13, x0, Operand(x1, SXTX, 3));
666 __ Orn(x13, x0, Operand(x1, SXTX, 3));
735 __ And(x13, x0, Operand(x1, SXTX, 3));
876 __ Bic(x13, x0, Operand(x1, SXTX, 3));
1004 __ Eor(x13, x0, Operand(x1, SXTX, 3));
1073 __ Eon(x13, x0, Operand(x1, SXTX, 3));
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | 347 COMPARE(adds(x27, x28, Operand(x29, SXTX)), "adds x27, x28, x29, sxtx");
373 COMPARE(subs(x27, x28, Operand(x29, SXTX)), "subs x27, x28, x29, sxtx");
[all...] |
| test-assembler-a64.cc | 528 __ Orr(x13, x0, Operand(x1, SXTX, 3));
617 __ Orn(x13, x0, Operand(x1, SXTX, 3));
684 __ And(x13, x0, Operand(x1, SXTX, 3));
822 __ Bic(x13, x0, Operand(x1, SXTX, 3));
946 __ Eor(x13, x0, Operand(x1, SXTX, 3));
1013 __ Eon(x13, x0, Operand(x1, SXTX, 3));
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| assembler-arm64-inl.h | 360 // Extend modes SXTX and UXTX require a 64-bit register.
361 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
475 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
477 // SXTX extend mode requires a 64-bit offset register.
478 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
528 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
529 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
[all...] |
| disasm-arm64.cc | 148 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
150 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
[all...] |
| constants-arm64.h | 349 SXTX = 7
[all...] |
| simulator-arm64.cc | 942 case SXTX:
[all...] |
| macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
[all...] |
| assembler-arm64.cc | [all...] |
| /external/vixl/src/a64/ |
| assembler-a64.cc | 234 // Extend modes SXTX and UXTX require a 64-bit register.
235 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
285 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
287 // SXTX extend mode requires a 64-bit offset register.
288 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX));
336 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
337 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX)));
[all...] |
| disasm-a64.cc | 155 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
157 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
[all...] |
| macro-assembler-a64.cc | 199 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
703 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
[all...] |
| simulator-a64.cc | 354 case SXTX:
764 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
[all...] |
| constants-a64.h | 239 SXTX = 7
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 954 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
962 // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
964 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
970 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
979 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) &&
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 466 SXTX
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 566 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
[all...] |
