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Searched
refs:Stall
(Results
1 - 15
of
15
) sorted by null
/external/oprofile/events/mips/rm9000/
events
12
event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES :
Stall
cycles
24
event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss
stall
cycles
30
event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES :
Stall
cycles due to a full write buffer
31
event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES :
Stall
cycles due to cache instructions
32
event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES :
Stall
cycles due to pending non-blocking loads -
stall
start of exception
/external/oprofile/events/mips/rm7000/
events
13
event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES :
Stall
cycles
25
event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss
stall
cycles (cycles where both cache miss tokens taken and a third try is requested)
31
event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full
stall
cycles
32
event:0x1d counters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction
stall
cycles
33
event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier
stall
cycles
34
event:0x1f counters:0,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD :
Stall
cycles due to pending non-blocking loads -
stall
start of exception
/external/tremolo/Tremolo/
bitwiseARM.s
89
@
Stall
90
@
Stall
93
@
Stall
94
@
Stall
107
@
Stall
135
@
stall
136
@
stall
139
@
stall
140
@
stall
147
@
stall
[
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...]
mdctARM.s
98
@
stall
99
@
stall
(Xscale)
166
@
stall
167
@
stall
(Xscale)
327
@
stall
328
@
stall
?
331
@
stall
?
334
@
stall
?
351
@
stall
352
@
stall
[
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/external/oprofile/events/mips/24K/
events
36
event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0
Stall
cycles, including ALU and IFU
43
event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU
stall
cycles
53
# Count number of cycles (most often ``
stall
cycles'', ie time lost), not just number of events.
55
event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0
Stall
cycles due to an instruction cache miss
56
event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC
stall
cycles
58
event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached
stall
cycles
59
event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU
stall
cycles
60
event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2
stall
cycles
61
event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM
stall
cycles
62
event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0
Stall
cycless due to CACHE instruction
[
all
...]
/external/oprofile/events/mips/34K/
events
36
event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0
Stall
cycles, including ALU and IFU
43
event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU
stall
cycles
57
# Count number of cycles (most often ``
stall
cycles'', ie time lost), not just number of events.
59
event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0
Stall
cycles due to an instruction cache miss
62
event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached
stall
cycles
63
event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU
stall
cycles
64
event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2
stall
cycles
65
event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM
stall
cycles
66
event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0
Stall
cycless due to CACHE instructions
67
event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use
stall
cycle
[
all
...]
/external/chromium_org/third_party/opus/src/celt/arm/
celt_pitch_xcorr_arm.s
278
;
Stall
310
;
Stall
391
;
Stall
464
;
Stall
475
;
Stall
525
;
Stall
532
;
Stall
/external/libopus/celt/arm/
celt_pitch_xcorr_arm.s
278
;
Stall
310
;
Stall
391
;
Stall
464
;
Stall
475
;
Stall
525
;
Stall
532
;
Stall
/external/oprofile/events/mips/1004K/
events
36
event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0
Stall
cycles, including ALU and IFU
43
event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU
stall
cycles
55
event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing
stall
cycles
58
# Count number of cycles (most often ``
stall
cycles'', ie time lost), not just number of events.
60
event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0
Stall
cycles due to an instruction cache miss
63
event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached
stall
cycles
64
event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU
stall
cycles
65
event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2
stall
cycles
66
event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM
stall
cycles
67
event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0
Stall
cycless due to CACHE instruction
[
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/frameworks/base/media/tests/MediaFrameworkTest/src/com/android/mediaframeworktest/unit/
CameraMetadataTest.java
[
all
...]
/external/llvm/include/llvm/CodeGen/
MachineScheduler.h
625
// Remember the greatest possible
stall
as an upper bound on the number of
748
NoCand, PhysRegCopy, RegExcess, RegCritical,
Stall
, Cluster, Weak, RegMax,
/external/oprofile/events/i386/westmere/
unit_masks
95
0x01 lcp Length Change Prefix
stall
cycles
96
0x02 mru
Stall
cycles due to BPU MRU bypass
97
0x04 iq_full Instruction Queue full
stall
cycles
98
0x08 regen Regen
stall
cycles
99
0x0f any Any Instruction Length Decoder
stall
cycles
128
0x04 cycles_stalled L1I instruction fetch
stall
cycles
231
0x01 flags Flag
stall
cycles
232
0x02 registers Partial register
stall
cycles
234
0x08 scoreboard Scoreboard
stall
cycles
235
0x0f any All RAT
stall
cycle
[
all
...]
/external/oprofile/events/mips/74K/
events
21
event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0
Stall
cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
25
event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss
stall
cycles
26
event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch
stall
cycles
31
event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage
stall
cycles due to DDQ0 (ALU out-of-order dispatch queue) full
32
event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage
stall
cycles due to ALCB (ALU completion buffers) full
33
event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage
stall
cycles due to CLDQ (data comming back from FPU) full
48
event:0x1e counters:0,2 um:zero minimum:500 name:FSB_FULL_STALLS : 30-0 Pipe
stall
cycles due to FSB full
49
event:0x1f counters:0,2 um:zero minimum:500 name:LDQ_FULL_STALLS : 31-0 Pipe
stall
cycles due to LDQ full
50
event:0x20 counters:0,2 um:zero minimum:500 name:WBB_FULL_STALLS : 32-0 Pipe
stall
cycles due to WBB full
107
event:0x40d counters:1,3 um:zero minimum:500 name:DDQ1_FULL_DR_STALLS : 13-1 DR stage
stall
cycles due to DDQ1 (AGEN out-of-order dispatch queue) ful
[
all
...]
/external/llvm/lib/CodeGen/
MachineScheduler.cpp
[
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...]
/external/chromium-trace/
script.js
[
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