| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 100 static bool isGPR64(unsigned Reg, unsigned SubReg,
102 if (SubReg)
109 static bool isFPR64(unsigned Reg, unsigned SubReg,
113 SubReg == 0) ||
115 SubReg == AArch64::dsub);
117 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
118 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
125 unsigned &SubReg) {
126 SubReg = 0;
134 SubReg = AArch64::dsub
[all...] |
| AArch64ISelDAGToDAG.cpp | 526 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
528 SDLoc(N), MVT::i32, N, SubReg);
665 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
670 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
[all...] |
| AArch64InstrInfo.cpp | [all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 198 unsigned SubReg = *SubRegs;
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs;
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg = *SubRegs
[all...] |
| MachineInstrBundle.cpp | 175 unsigned SubReg = *SubRegs;
176 if (LocalDefSet.insert(SubReg))
177 LocalDefs.push_back(SubReg);
|
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
44 if (*Subs == SubReg)
|
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 90 unsigned SubReg) const;
94 unsigned SubReg) const;
137 unsigned SubReg) const {
144 RC = TRI->getSubRegClass(RC, SubReg);
163 unsigned SubReg) const {
166 return TRI->getSubRegClass(RC, SubReg);
170 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
|
| SILowerControlFlow.cpp | 407 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
408 if (!SubReg)
409 SubReg = Vec;
413 .addReg(SubReg + Off)
428 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
429 if (!SubReg)
430 SubReg = Dst;
434 .addReg(SubReg + Off, RegState::Define)
|
| R600OptimizeVectorRegisters.cpp | 12 /// common data and/or have enough undef subreg using swizzle abilities.
191 unsigned SubReg = (*It).first;
198 .addReg(SubReg)
200 UpdatedRegToChan[SubReg] = Chan;
|
| SIInstrInfo.cpp | 328 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
334 .addReg(SubReg)
352 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
356 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
396 unsigned SubReg = MI->getOperand(1).getSubReg();
399 MI->getOperand(2).setSubReg(SubReg);
788 unsigned SubReg = MRI.createVirtualRegister(SubRC);
791 // value so we don't need to worry about merging its subreg index with the
799 SubReg)
801 return SubReg;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 224 const char *const *SubRegIndexNames; // Names of subreg indexes.
496 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
501 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 107 // Return true if any CC result of MI would reflect the value of subreg
108 // SubReg of Reg.
109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) {
114 MI->getOperand(0).getSubReg() == SubReg)
131 MI->getOperand(1).getSubReg() == SubReg)
|
| SystemZISelLowering.h | 303 bool ClearEven, unsigned SubReg) const;
|
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 65 unsigned SubReg = 0) const {
75 SubReg,
|
| MachineOperand.h | 71 /// MO_Register has no subReg.
344 void setSubReg(unsigned subReg) {
346 SubReg_TargetFlags = subReg;
347 assert(SubReg_TargetFlags == subReg && "SubReg out of range");
351 /// subregister Reg:SubReg. Take any existing SubReg index into account,
352 /// using TargetRegisterInfo to compose the subreg indices if necessary.
358 /// Reg, taking any existing SubReg into account. For instance,
580 unsigned SubReg = 0
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
536 BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
539 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 460 /// EmitSubregNode - Generate machine code for subreg nodes.
619 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
620 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
712 // Handle subreg insert/extract specially
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 347 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
349 O << ARMInstPrinter::getRegisterName(SubReg);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 257 // Expand any composed subreg indices.
259 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
260 // expanded subreg indices recursively.
275 // Add I->second as a name for the subreg SRI->second, assuming it is
288 // Consider this subreg sequence:
299 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
311 // Compute the inverse SubReg -> Idx map.
429 const CodeGenRegister *SubReg = I->second;
430 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs
[all...] |
