/external/llvm/include/llvm/Target/ |
TargetOpcodes.h | 24 namespace TargetOpcode { 109 } // end namespace TargetOpcode
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/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 680 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 681 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 687 return getOpcode() == TargetOpcode::CFI_INSTRUCTION; 693 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 702 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } 703 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 704 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 705 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 707 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect(); 712 return getOpcode() == TargetOpcode::INSERT_SUBREG [all...] |
/external/llvm/lib/CodeGen/ |
ExpandPostRAPseudos.cpp | 102 MI->setDesc(TII->get(TargetOpcode::KILL)); 113 MI->setDesc(TII->get(TargetOpcode::KILL)); 140 MI->setDesc(TII->get(TargetOpcode::KILL)); 155 MI->setDesc(TII->get(TargetOpcode::KILL)); 210 case TargetOpcode::SUBREG_TO_REG: 213 case TargetOpcode::COPY: 216 case TargetOpcode::DBG_VALUE: 218 case TargetOpcode::INSERT_SUBREG: 219 case TargetOpcode::EXTRACT_SUBREG:
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ErlangGC.cpp | 58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
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StackColoring.cpp | 247 if (MI.getOpcode() != TargetOpcode::LIFETIME_START && 248 MI.getOpcode() != TargetOpcode::LIFETIME_END) 253 bool IsStart = MI.getOpcode() == TargetOpcode::LIFETIME_START; 388 assert((MI->getOpcode() == TargetOpcode::LIFETIME_START || 389 MI->getOpcode() == TargetOpcode::LIFETIME_END) && 392 bool IsStart = MI->getOpcode() == TargetOpcode::LIFETIME_START; 507 if (I.getOpcode() == TargetOpcode::LIFETIME_START || 508 I.getOpcode() == TargetOpcode::LIFETIME_END) 581 if (I.getOpcode() == TargetOpcode::LIFETIME_START || 582 I.getOpcode() == TargetOpcode::LIFETIME_END || I.isDebugValue() [all...] |
MachineSSAUpdater.cpp | 151 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, 188 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, 288 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, 300 MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc,
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StackMapLivenessAnalysis.cpp | 95 if (I->getOpcode() == TargetOpcode::PATCHPOINT) {
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/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 53 case TargetOpcode::EXTRACT_SUBREG: 54 case TargetOpcode::INSERT_SUBREG: 55 case TargetOpcode::SUBREG_TO_REG: 56 case TargetOpcode::REG_SEQUENCE: 57 case TargetOpcode::IMPLICIT_DEF: 58 case TargetOpcode::COPY: 59 case TargetOpcode::INLINEASM: 105 case TargetOpcode::EXTRACT_SUBREG: 106 case TargetOpcode::INSERT_SUBREG: 107 case TargetOpcode::SUBREG_TO_REG [all...] |
HexagonAsmPrinter.cpp | 185 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE || 186 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
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HexagonNewValueJump.cpp | 129 if (II->getOpcode() == TargetOpcode::KILL) 193 if (MII->getOpcode() == TargetOpcode::KILL || 194 MII->getOpcode() == TargetOpcode::PHI || 195 MII->getOpcode() == TargetOpcode::COPY) 249 if (def->getOpcode() == TargetOpcode::COPY)
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 282 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 293 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 335 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 455 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 481 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 503 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 519 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 521 } else if (Opc == TargetOpcode::INSERT_SUBREG | [all...] |
ResourcePriorityQueue.cpp | 265 case TargetOpcode::EXTRACT_SUBREG: 266 case TargetOpcode::INSERT_SUBREG: 267 case TargetOpcode::SUBREG_TO_REG: 268 case TargetOpcode::REG_SEQUENCE: 269 case TargetOpcode::IMPLICIT_DEF: 305 case TargetOpcode::EXTRACT_SUBREG: 306 case TargetOpcode::INSERT_SUBREG: 307 case TargetOpcode::SUBREG_TO_REG: 308 case TargetOpcode::REG_SEQUENCE: 309 case TargetOpcode::IMPLICIT_DEF [all...] |
FastISel.cpp | 237 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 324 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 650 TII.get(TargetOpcode::STACKMAP)); 681 TII.get(TargetOpcode::INLINEASM)) 752 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0, 756 TII.get(TargetOpcode::DBG_VALUE)) 770 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcCodeEmitter.cpp | 141 case TargetOpcode::INLINEASM: { 149 case TargetOpcode::CFI_INSTRUCTION: 151 case TargetOpcode::EH_LABEL: { 155 case TargetOpcode::IMPLICIT_DEF: 156 case TargetOpcode::KILL: {
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SparcFrameLowering.cpp | 118 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 131 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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/external/llvm/lib/Target/MSP430/ |
MSP430InstrInfo.cpp | 302 case TargetOpcode::CFI_INSTRUCTION: 303 case TargetOpcode::EH_LABEL: 304 case TargetOpcode::IMPLICIT_DEF: 305 case TargetOpcode::KILL: 306 case TargetOpcode::DBG_VALUE: 308 case TargetOpcode::INLINEASM: {
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/external/llvm/lib/Target/AArch64/ |
AArch64CleanupLocalDynamicTLSPass.cpp | 102 TII->get(TargetOpcode::COPY), 126 TII->get(TargetOpcode::COPY),
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/external/llvm/lib/Target/PowerPC/ |
PPCCodeEmitter.cpp | 126 case TargetOpcode::CFI_INSTRUCTION: 128 case TargetOpcode::EH_LABEL: 131 case TargetOpcode::IMPLICIT_DEF: 132 case TargetOpcode::KILL:
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/external/llvm/lib/Target/Mips/ |
MipsSEFrameLowering.cpp | 111 case TargetOpcode::COPY: 139 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) 158 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) 184 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); 253 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) 256 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) 308 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 339 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 344 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 350 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION) [all...] |
Mips16FrameLowering.cpp | 57 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 72 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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/external/llvm/lib/Target/ARM/ |
Thumb1FrameLowering.cpp | 123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 134 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 198 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 225 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 243 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 249 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 266 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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ARMFrameLowering.cpp | 199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 211 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 376 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 401 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 422 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 429 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 440 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 457 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 474 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 488 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIAssignInterpRegs.cpp | 131 TII->get(TargetOpcode::COPY), virtReg)
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIAssignInterpRegs.cpp | 131 TII->get(TargetOpcode::COPY), virtReg)
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/external/llvm/lib/Target/R600/ |
AMDGPUISelDAGToDAG.cpp | 322 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 354 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, 383 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N), 666 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 668 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 671 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, 673 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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