/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 517 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, 521 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, 525 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, 529 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, 534 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, 538 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, 542 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, 546 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 181 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::UREM, MVT::i32, Expand);
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AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines 725 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::UREM, MVT::i32, Expand);
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AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines 725 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.h | 703 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
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SelectionDAGDumper.cpp | 169 case ISD::UREM: return "urem";
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FastISel.cpp | 420 // Transform "urem x, pow2" -> "and x, pow2-1". 421 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && [all...] |
LegalizeVectorOps.cpp | 244 case ISD::UREM: [all...] |
LegalizeVectorTypes.cpp | 118 case ISD::UREM: 640 case ISD::UREM: [all...] |
SelectionDAG.cpp | [all...] |
LegalizeIntegerTypes.cpp | 115 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; [all...] |
LegalizeDAG.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 153 setOperationAction(ISD::UREM, MVT::i8, Expand); 159 setOperationAction(ISD::UREM, MVT::i16, Expand); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 171 setOperationAction(ISD::UREM, MVT::i32, Legal); 216 setOperationAction(ISD::UREM, MVT::i64, Legal); 270 setOperationAction(ISD::UREM, Ty, Legal); [all...] |
MipsISelLowering.cpp | 284 setOperationAction(ISD::UREM, MVT::i32, Expand); 288 setOperationAction(ISD::UREM, MVT::i64, Expand); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | [all...] |
AArch64ISelLowering.cpp | 255 setOperationAction(ISD::UREM, MVT::i32, Expand); 256 setOperationAction(ISD::UREM, MVT::i64, Expand); 533 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); [all...] |
/external/llvm/lib/Target/R600/ |
AMDGPUISelLowering.cpp | 279 setOperationAction(ISD::UREM, MVT::i32, Expand); 303 // TODO: Implement custom UREM / SREM routines. 307 setOperationAction(ISD::UREM, VT, Expand); [all...] |
R600ISelLowering.cpp | 161 setOperationAction(ISD::UREM, MVT::i64, Custom); 853 case ISD::UREM: { [all...] |
SIISelLowering.cpp | 174 setOperationAction(ISD::UREM, MVT::i64, Expand); [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | [all...] |