| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 43 UXTX,
63 case AArch64_AM::UXTX: return "uxtx";
130 case 3: return AArch64_AM::UXTX;
146 /// 011 ==> uxtx
157 case AArch64_AM::UXTX: return 3; break;
193 /// 011 ==> uxtx
|
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.cc | 148 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
150 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
[all...] |
| assembler-arm64-inl.h | 360 // Extend modes SXTX and UXTX require a 64-bit register.
361 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
392 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
[all...] |
| constants-arm64.h | 345 UXTX = 3,
[all...] |
| assembler-arm64.cc | [all...] |
| simulator-arm64.cc | 941 case UXTX:
[all...] |
| macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
[all...] |
| /external/vixl/src/a64/ |
| disasm-a64.cc | 155 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
157 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
[all...] |
| assembler-a64.cc | 234 // Extend modes SXTX and UXTX require a 64-bit register.
235 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
266 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
[all...] |
| macro-assembler-a64.cc | 199 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
703 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
[all...] |
| simulator-a64.cc | 353 case UXTX:
764 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
[all...] |
| constants-a64.h | 235 UXTX = 3,
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 954 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
962 // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
964 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
970 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm64.cc | 381 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4");
393 COMPARE(cmn(csp, Operand(xzr, UXTX, 3)), "cmn csp, xzr, lsl #3");
407 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4");
419 COMPARE(cmp(csp, Operand(xzr, UXTX, 3)), "cmp csp, xzr, lsl #3");
[all...] |
| test-assembler-arm64.cc | 565 __ Orr(x9, x0, Operand(x1, UXTX, 3));
662 __ Orn(x9, x0, Operand(x1, UXTX, 3));
731 __ And(x9, x0, Operand(x1, UXTX, 3));
872 __ Bic(x9, x0, Operand(x1, UXTX, 3));
1000 __ Eor(x9, x0, Operand(x1, UXTX, 3));
1069 __ Eon(x9, x0, Operand(x1, UXTX, 3));
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | 342 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4");
354 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3");
368 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4");
380 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3");
[all...] |
| test-assembler-a64.cc | 524 __ Orr(x9, x0, Operand(x1, UXTX, 3));
613 __ Orn(x9, x0, Operand(x1, UXTX, 3));
680 __ And(x9, x0, Operand(x1, UXTX, 3));
818 __ Bic(x9, x0, Operand(x1, UXTX, 3));
942 __ Eor(x9, x0, Operand(x1, UXTX, 3));
1009 __ Eon(x9, x0, Operand(x1, UXTX, 3));
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 461 UXTX,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | 566 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
[all...] |
