| /art/runtime/arch/arm64/ |
| registers_arm64.cc | 28 "lr", "sp", "xzr"
39 if (rhs >= X0 && rhs <= XZR) {
|
| registers_arm64.h | 67 XZR = 32,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 106 NewReg = AArch64::XZR;
|
| AArch64A53Fix835769.cpp | 70 // non-accumulating multiplies, i.e. when Ra=XZR='11111'
71 return MI->getOperand(3).getReg() != AArch64::XZR;
|
| AArch64RegisterInfo.cpp | 84 Reserved.set(AArch64::XZR);
114 case AArch64::XZR:
380 return 32 - 1 // XZR/SP
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| AArch64ExpandPseudoInsts.cpp | 100 .addReg(AArch64::XZR)
167 .addReg(AArch64::XZR)
350 .addReg(AArch64::XZR)
405 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
434 // ORR x0, xzr, |A|X|A|X|
|
| AArch64InstrInfo.cpp | 334 // not x -> csinv, represented as orn dst, xzr, src.
336 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
351 // neg x -> csneg, represented as sub dst, xzr, src.
353 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
450 // cmp reg, #0 is actually subs xzr, reg, #0.
452 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
479 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
486 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
986 return MI->getOperand(1).getReg() == AArch64::XZR;
1005 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0
[all...] |
| AArch64AsmPrinter.cpp | 287 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
|
| AArch64ConditionalCompares.cpp | 260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
|
| AArch64FastISel.cpp | 932 ZReg = AArch64::XZR;
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64.h | 193 return IsCoreRegister() && (id_ == XZR);
|
| assembler_arm64.h | 201 } else if (code == XZR) {
202 return vixl::xzr;
|
| managed_register_arm64_test.cc | 300 EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromCoreRegister(XZR)));
309 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromCoreRegister(XZR)));
453 reg = Arm64ManagedRegister::FromCoreRegister(XZR);
464 EXPECT_NE(XZR, reg_o.AsOverlappingWRegisterCore());
[all...] |
| assembler_arm64.cc | 210 ___ Csel(reg_x(dest), reg_x(XZR), reg_x(dest), COND_OP(cond));
|
| /external/llvm/test/MC/AArch64/ |
| arm64-aliases.s | 27 orr x2, xzr, x9
44 ands xzr, x1, x2, lsl #3
58 ; ADDS to WZR/XZR is a CMN
80 ; SUBS to WZR/XZR is a CMP
110 ; SUB/SUBS from WZR/XZR is a NEG
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 653 if (Reg != AArch64::XZR)
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 63 case AArch64::XZR: return AArch64::WZR;
103 case AArch64::WZR: return AArch64::XZR;
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 376 AArch64::LR, AArch64::XZR
396 if (Register == AArch64::XZR)
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
