/external/qemu/include/exec/ |
gen-icount.h | 20 tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32)); 26 tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low)); 42 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); 49 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
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/external/qemu/target-mips/ |
translate.c | 428 static TCGv_ptr cpu_env; variable 564 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 569 tcg_gen_add_ptr(addr, cpu_env, addr); 587 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 592 tcg_gen_add_ptr(addr, cpu_env, addr); 604 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); 609 tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); 614 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); 619 tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); 625 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d)) [all...] |
/external/qemu/target-i386/ |
translate.c | 76 static TCGv_ptr cpu_env; variable 365 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_B_OFFSET); 367 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg - 4]) + REG_H_OFFSET); 371 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_W_OFFSET); 375 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_L_OFFSET); 378 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_LH_OFFSET); 382 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg])); 387 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_L_OFFSET); 407 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_W_OFFSET); 411 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUX86State, regs[reg]) + REG_L_OFFSET) [all...] |
/external/qemu/target-arm/ |
translate.c | 85 static TCGv_ptr cpu_env; variable 112 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 136 tcg_gen_ld_i32(tmp, cpu_env, offset); 144 tcg_gen_st_i32(var, cpu_env, offset); 200 gen_helper_cpsr_write(cpu_env, var, tmp_mask); 210 gen_helper_exception(cpu_env, tmp); 370 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, CF)) 384 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, NF)); 385 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, ZF)); 491 case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break [all...] |
/external/qemu/hw/intc/ |
apic.c | 67 CPUOldState *cpu_env; member in struct:APICState 243 cpu_interrupt(ENV_GET_CPU(apic_iter->cpu_env), CPU_INTERRUPT_SMI) ); 248 cpu_interrupt(ENV_GET_CPU(apic_iter->cpu_env), CPU_INTERRUPT_NMI) ); 254 cpu_interrupt(ENV_GET_CPU(apic_iter->cpu_env), CPU_INTERRUPT_INIT) ); 369 cpu_interrupt(ENV_GET_CPU(s->cpu_env), CPU_INTERRUPT_HARD); 491 cpu_interrupt(ENV_GET_CPU(s->cpu_env), CPU_INTERRUPT_SIPI); 647 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); 908 int bsp = cpu_is_bsp(s->cpu_env); 913 cpu_reset(ENV_GET_CPU(s->cpu_env)); 914 apic_init_reset(s->cpu_env); [all...] |