| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_SC32_Radix2_ls_unsafe_s.S | 77 #define dXi1 d5.s32
105 VLD4 {dXr0,dXi0,dXr1,dXi1},[pSrc :128]!
110 VMLAL qT0,dWi,dXi1 @// real part
111 VMULL qT1,dWr,dXi1
117 VMLSL qT0,dWi,dXi1 @// real part
118 VMULL qT1,dWr,dXi1
124 VRSHRN dXi1,qT1,#31
130 VHSUB dYi0,dXi0,dXi1
132 VHADD dYi1,dXi0,dXi1
137 VSUB dYi0,dXi0,dXi1
[all...] |
| armSP_FFT_CToC_SC16_Radix2_ls_unsafe_s.S | 85 #define dXi1 D5.S16
119 VLD4 {dXr0[0],dXi0[0],dXr1[0],dXi1[0]},[pSrc]! @// grp 0
120 VLD4 {dXr0[1],dXi0[1],dXr1[1],dXi1[1]},[pSrc]! @// grp 1
123 @//VLD4 {dXr0,dXi0,dXr1,dXi1},[pSrc],#32
128 VMLAL qT0,dXi1,dWi @// real part
129 VMULL qT1,dXi1,dWr
134 VMLSL qT0,dXi1,dWi @// real part
135 VMULL qT1,dXi1,dWr
141 VRSHRN dXi1,qT1,#15
147 VHSUB dYi0,dXi0,dXi1
[all...] |
| armSP_FFT_CToC_FC32_Radix2_ls_unsafe_s.S | 68 #define dXi1 d5.f32
101 @ dXi1 = [pSrc[1].Im, pSrc[3].Im]
102 VLD4 {dXr0,dXi0,dXr1,dXi1},[pSrc :128]!
107 VMLA qT0,dWi,dXi1 @// real part
108 VMUL qT1,dWr,dXi1
114 VMLS qT0,dWi,dXi1 @// real part
115 VMUL qT1,dWr,dXi1
|
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 86 #define dXi1 D7.F32
167 VLD2 {dXr1,dXi1},[pSrc],pointStep @// data[1]
192 VMUL dZi1,dXi1,dW1[0]
198 VMLA dZr1,dXi1,dW1[1] @// real part
202 VLD2 {dXr1,dXi1},[pSrc],pointStep
214 VMUL dZi1,dXi1,dW1[0]
220 VMLS dZr1,dXi1,dW1[1] @// real part
224 VLD2 {dXr1,dXi1},[pSrc],pointStep
|
| armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 93 #define dXi1 D7.S16
182 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
189 VMLAL qT0,dXi1,dW1[1] @// real part
190 VMULL qT1,dXi1,dW1[0]
195 VMLSL qT0,dXi1,dW1[1] @// real part
196 VMULL qT1,dXi1,dW1[0]
|
| armSP_FFT_CToC_SC32_Radix4_fs_unsafe_s.S | 82 #define dXi1 D3.S32
134 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
182 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
204 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
244 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
266 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
|
| armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 74 #define dXi1 D3.F32
127 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
176 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
203 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
|
| armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 82 #define dXi1 D3.S16
133 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
178 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
232 VLD2 {dXr1,dXi1},[pSrc :128],step1 @// data[1]
|
| armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 95 #define dXi1 D7.S32
175 VLD2 {dXr1,dXi1},[pSrc],pointStep @// data[1]
198 VMLAL qT0,dXi1,dW1[1] @// real part
199 VMULL qT1,dXi1,dW1[0]
204 VMLSL qT0,dXi1,dW1[1] @// real part
205 VMULL qT1,dXi1,dW1[0]
210 VLD2 {dXr1,dXi1},[pSrc],pointStep @// data[1] for next iteration
|
| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 82 #define dXi1 D3.F32
194 VMLA dZr1,dW1i,dXi1 @// real part
195 VMUL dZi1,dW1r,dXi1
201 VMLS dZr1,dW1i,dXi1 @// real part
202 VMUL dZi1,dW1r,dXi1
|
| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 97 #define dXi1 D3.S16
217 VMLAL qT0,dXi1,dW1i @// real part
218 VMULL qT1,dXi1,dW1r
223 VMLSL qT0,dXi1,dW1i @// real part
224 VMULL qT1,dXi1,dW1r
|
| armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 90 #define dXi1 D3.S32
199 VMLAL qT0,dW1i,dXi1 @// real part
200 VMULL qT1,dW1r,dXi1
206 VMLSL qT0,dW1i,dXi1 @// real part
207 VMULL qT1,dW1r,dXi1
|
| armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 74 #define dXi1 D3.F32
204 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
293 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
|
| armSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S | 85 #define dXi1 D3.S16
225 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
314 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
476 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
|
| armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S | 84 #define dXi1 D3.S32
218 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
305 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
464 VLD2 {dXr1,dXi1},[pSrc :128],pointStep @// data[1]
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFT_CToC_FC32_Radix2_ls_s.S | 69 #define dXi1 v5.2s
104 // dXi1 = [pSrc[1].Im, pSrc[3].Im]
105 ld4 {dXr0,dXi0,dXr1,dXi1}, [pSrc], #32
111 fmla qT0,dWi,dXi1 // real part
112 fmul qT1,dWr,dXi1
118 fmls qT0,dWi,dXi1 // real part
119 fmul qT1,dWr,dXi1
|
| armSP_FFT_CToC_FC32_Radix4_s.S | 89 #define dXi1 v7.2s
160 ld2 {dXr1,dXi1},[pSrc],pointStep // data[1]
186 fmul dZi1,dXi1,dW1[0]
192 fmla dZr1,dXi1,dW1[1] // real part
196 ld2 {dXr1,dXi1},[pSrc],pointStep
208 fmul dZi1,dXi1,dW1[0]
214 fmls dZr1,dXi1,dW1[1] // real part
218 ld2 {dXr1,dXi1},[pSrc],pointStep
|
| armSP_FFT_CToC_FC32_Radix4_fs_s.S | 74 #define dXi1 v3.2s
119 ld2 {dXr1,dXi1}, [pSrc], pointStep // data[1]
166 fadd dYi1, dXi1, dXi3
170 fsub dYi3, dXi1, dXi3
177 ld2 {dXr1,dXi1}, [pSrc], step1 // data[1]
211 ld2 {dXr1,dXi1}, [pSrc], step1 // data[1]
|
| armSP_FFT_CToC_FC32_Radix4_ls_s.S | 89 #define dXi1 v3.2s
217 fmla dZr1,dW1i,dXi1 // real part
218 fmul dZi1,dW1r,dXi1
224 fmls dZr1,dW1i,dXi1 // real part
225 fmul dZi1,dW1r,dXi1
|
| armSP_FFT_CToC_FC32_Radix8_fs_s.S | 74 #define dXi1 v3.2s
210 ld2 {dXr1,dXi1},[pSrc],pointStep // data[1]
243 fadd dUi2,dXi1,dXi5
292 fsub dUi3,dXi1,dXi5
317 fsub dUi3,dXi1,dXi5
340 ld2 {dXr1,dXi1},[pSrc],pointStep // data[1]
|
