| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFT_CToC_FC32_Radix4_fs_s.S | 78 #define dXi3 v7.2s
134 ld2 {dXr3,dXi3}, [pSrc], setStep
166 fadd dYi1, dXi1, dXi3
170 fsub dYi3, dXi1, dXi3
186 ld2 {dXr3,dXi3}, [pSrc], setStep
220 ld2 {dXr3,dXi3}, [pSrc], setStep
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| armSP_FFT_CToC_FC32_Radix4_s.S | 93 #define dXi3 v11.2s
167 ld2 {dXr3,dXi3},[pSrc],setStep
190 fmul dZi3,dXi3,dW3[0]
204 fmla dZr3,dXi3,dW3[1] // real part
212 fmul dZi3,dXi3,dW3[0]
226 fmls dZr3,dXi3,dW3[1] // real part
241 ld2 {dXr3,dXi3},[pSrc],setStep
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| armSP_FFT_CToC_FC32_Radix4_ls_s.S | 93 #define dXi3 v7.2s
259 fmla dZr3,dW3i,dXi3 // real part
260 fmul dZi3,dW3r,dXi3
267 fmls dZr3,dW3i,dXi3 // real part
268 fmul dZi3,dW3r,dXi3
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| armSP_FFT_CToC_FC32_Radix8_fs_s.S | 78 #define dXi3 v7.2s
216 ld2 {dXr3,dXi3},[pSrc],pointStep // data[3]
245 fadd dUi6,dXi3,dXi7
329 fsub dUi7,dXi3,dXi7
347 ld2 {dXr3,dXi3},[pSrc],pointStep // data[3]
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| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 90 #define dXi3 D11.F32
174 VLD2 {dXr3,dXi3},[pSrc],setStep
196 VMUL dZi3,dXi3,dW3[0]
210 VMLA dZr3,dXi3,dW3[1] @// real part
218 VMUL dZi3,dXi3,dW3[0]
232 VMLS dZr3,dXi3,dW3[1] @// real part
244 VLD2 {dXr3,dXi3},[pSrc],setStep
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| armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 97 #define dXi3 D11.S16
215 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3] & update pSrc for the next set
225 VMLAL qT0,dXi3,dW3[1] @// real part
226 VMULL qT1,dXi3,dW3[0]
231 VMLSL qT0,dXi3,dW3[1] @// real part
232 VMULL qT1,dXi3,dW3[0]
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| armSP_FFT_CToC_SC32_Radix4_fs_unsafe_s.S | 86 #define dXi3 D7.S32
145 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3] & update pSrc for the next set
185 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3] & update pSrc for the next set
207 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3] & update pSrc for the next set
247 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3] & update pSrc for the next set
269 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3] & update pSrc for the next set
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| armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 78 #define dXi3 D7.F32
141 VLD2 {dXr3,dXi3},[pSrc :128],setStep
183 VLD2 {dXr3,dXi3},[pSrc :128],setStep
210 VLD2 {dXr3,dXi3},[pSrc :128],setStep
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| armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 99 #define dXi3 D11.S32
180 VLD2 {dXr3,dXi3},[pSrc],setStep @// data[3] & update pSrc for the next set
233 VMLAL qT0,dXi3,dW3[1] @// real part
234 VMULL qT1,dXi3,dW3[0]
239 VMLSL qT0,dXi3,dW3[1] @// real part
240 VMULL qT1,dXi3,dW3[0]
251 VLD2 {dXr3,dXi3},[pSrc],setStep @// data[3] & update pSrc to data[0]
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| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 86 #define dXi3 D7.F32
234 VMLA dZr3,dW3i,dXi3 @// real part
235 VMUL dZi3,dW3r,dXi3
242 VMLS dZr3,dW3i,dXi3 @// real part
243 VMUL dZi3,dW3r,dXi3
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| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 101 #define dXi3 D7.S16
253 VMLAL qT0,dXi3,dW3i @// real part
254 VMULL qT1,dXi3,dW3r
259 VMLSL qT0,dXi3,dW3i @// real part
260 VMULL qT1,dXi3,dW3r
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| armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 94 #define dXi3 D7.S32
242 VMLAL qT4,dW3i,dXi3 @// real part
243 VMULL qT5,dW3r,dXi3
250 VMLSL qT4,dW3i,dXi3 @// real part
251 VMULL qT5,dW3r,dXi3
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| armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 86 #define dXi3 D7.S16
160 VLD2 {dXr3,dXi3},[pSrc :128],setStep @// data[3]
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| armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 78 #define dXi3 D7.F32
210 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
300 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
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| armSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S | 89 #define dXi3 D7.S16
232 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
321 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
483 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
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| armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S | 88 #define dXi3 D7.S32
223 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
312 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
471 VLD2 {dXr3,dXi3},[pSrc :128],pointStep @// data[3]
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