| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips64.cc | 171 COMPARE(ddivu(a0, a1),
172 "0085001f ddivu a0, a1");
173 COMPARE(ddivu(a6, a7),
174 "014b001f ddivu a6, a7");
175 COMPARE(ddivu(v0, v1),
176 "0043001f ddivu v0, v1");
263 COMPARE(ddivu(a0, a1, a2),
264 "00a6209f ddivu a0, a1, a2");
271 COMPARE(ddivu(a5, a6, a7),
272 "014b489f ddivu a5, a6, a7")
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
|
| /external/chromium_org/v8/src/mips64/ |
| disasm-mips64.cc | 840 case DDIVU: // @Mips64r6 == D_DIV_MOD_U.
842 Format(instr, "ddivu 'rs, 'rt");
845 Format(instr, "ddivu 'rd, 'rs, 'rt");
[all...] |
| assembler-mips64.h | 748 void ddivu(Register rs, Register rt);
752 void ddivu(Register rd, Register rs, Register rt);
[all...] |
| assembler-mips64.cc | 1603 void Assembler::ddivu(Register rs, Register rt) { function in class:v8::Assembler
1608 void Assembler::ddivu(Register rd, Register rs, Register rt) { function in class:v8::Assembler
[all...] |
| macro-assembler-mips64.cc | 867 void MacroAssembler::Ddivu(Register rs, const Operand& rt) {
869 ddivu(rs, rt.rm());
874 ddivu(rs, at);
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 19 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 54 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 56 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 56 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 61 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 62 ddivu $zero,$s0,$s1
|
| /external/openssl/crypto/bn/asm/ |
| mips3.s | 667 ddivu zero,a0,DH
700 ddivu zero,a0,DH
[all...] |
