| /external/openssl/crypto/bn/asm/ |
| mips3.s | 26 * 64-bit instructions (daddu, dmultu, etc.) found below gonna only
82 dmultu t0,a3
100 dmultu t2,a3
113 dmultu ta0,a3
128 dmultu ta2,a3
151 dmultu t0,a3
166 dmultu t0,a3
181 dmultu t0,a3
211 dmultu t0,a3
222 dmultu t2,a
[all...] |
| mips3-mont.pl | 94 dmultu $aj,$bi
99 dmultu $lo0,$n0
102 dmultu $alo,$bi
106 dmultu $nj,$m1
109 dmultu $nlo,$m1
126 dmultu $aj,$bi
138 dmultu $nj,$m1
177 dmultu $aj,$bi
183 dmultu $lo0,$n0
188 dmultu $alo,$b
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips64.cc | 141 COMPARE(dmultu(a0, a1),
142 "0085001d dmultu a0, a1");
145 COMPARE(dmultu(a6, a7),
146 "014b001d dmultu a6, a7");
149 COMPARE(dmultu(v0, v1),
150 "0043001d dmultu v0, v1");
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3.s | 13 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 17 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 22 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 25 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 24 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 26 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 27 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 26 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/src/mips64/ |
| disasm-mips64.cc | 773 case D_MUL_MUH_U: // Equals to DMULTU.
775 Format(instr, "dmultu 'rs, 'rt");
[all...] |
| assembler-mips64.h | 771 void dmultu(Register rs, Register rt);
[all...] |
| macro-assembler-mips64.cc | 794 void MacroAssembler::Dmultu(Register rs, const Operand& rt) {
796 dmultu(rs, rt.rm());
801 dmultu(rs, at);
[all...] |
| assembler-mips64.cc | 1581 void Assembler::dmultu(Register rs, Register rt) { function in class:v8::Assembler
[all...] |
| /external/qemu/target-mips/ |
| helper.h | 33 DEF_HELPER_2(dmultu, void, tl, tl)
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 62 dmultu $a1,$a2
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 64 dmultu $a1,$a2
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 64 dmultu $a1,$a2
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 69 dmultu $a1,$a2
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 70 dmultu $a1,$a2
|
