| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 25 * blend one of 2 16bpp RGB pixels held in dreg selected by shift
28 * Assumes that the dreg data is little endian and that
36 .macro pixel dreg src fb shift
52 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
54 ext $t0,\dreg,\shift+5,6 # start green extraction dst[\shift:10..5]
62 ext $t0,\dreg,\shift,5 # start blue extraction dst[\shift:4..0]
87 .macro pixel dreg src fb shift
112 srl $t8,\dreg,\shift+6+5
134 srl $t8,\dreg,\shift+5
146 srl $t8,\dreg,\shif
[all...] |
| /external/chromium_org/third_party/openmax_dl/dl/api/arm/ |
| arm64COMM_s.h | 35 .macro _M_GETDREGLIST dreg
36 .ifeqs "\dreg", ""
41 .ifeqs "\dreg", "d8"
46 .ifeqs "\dreg", "d9"
51 .ifeqs "\dreg", "d10"
56 .ifeqs "\dreg", "d11"
61 .ifeqs "\dreg", "d12"
66 .ifeqs "\dreg", "d13"
71 .ifeqs "\dreg", "d14"
76 .ifeqs "\dreg", "d15
[all...] |
| armCOMM_s.h | 97 .macro _M_GETDREGLIST dreg
98 .ifeqs "\dreg", ""
103 .ifeqs "\dreg", "d8"
108 .ifeqs "\dreg", "d9"
113 .ifeqs "\dreg", "d10"
118 .ifeqs "\dreg", "d11"
123 .ifeqs "\dreg", "d12"
128 .ifeqs "\dreg", "d13"
133 .ifeqs "\dreg", "d14"
138 .ifeqs "\dreg", "d15
[all...] |
| /external/vixl/examples/ |
| add3-double.cc | 68 printf("%f + %f + %f = %f\n", a, b, c, simulator.dreg(0));
|
| add4-double.cc | 78 printf("%ld + %f + %ld + %f = %f\n", a, b, c, d, simulator.dreg(0));
|
| /external/vixl/src/a64/ |
| simulator-a64.cc | 468 dreg(i),
813 case STR_d: MemoryWriteFP64(address, dreg(srcdst)); break;
895 MemoryWriteFP64(address, dreg(rt));
896 MemoryWriteFP64(address + kDRegSizeInBytes, dreg(rt2));
[all...] |
| simulator-a64.h | 323 inline double dreg(unsigned code) const {
334 case kDRegSize: return dreg(code);
|
| /external/chromium_org/v8/src/arm/ |
| simulator-arm.h | 141 void set_dw_register(int dreg, const int* dbl);
144 void get_d_register(int dreg, uint64_t* value);
145 void set_d_register(int dreg, const uint64_t* value);
146 void get_d_register(int dreg, uint32_t* value);
147 void set_d_register(int dreg, const uint32_t* value);
156 void set_d_register_from_double(int dreg, const double& dbl) {
157 SetVFPRegister<double, 2>(dreg, dbl);
160 double get_double_from_d_register(int dreg) {
161 return GetFromVFPRegister<double, 2>(dreg);
|
| simulator-arm.cc | 910 void Simulator::set_dw_register(int dreg, const int* dbl) {
911 DCHECK((dreg >= 0) && (dreg < num_d_registers));
912 registers_[dreg] = dbl[0];
913 registers_[dreg + 1] = dbl[1];
917 void Simulator::get_d_register(int dreg, uint64_t* value) {
918 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
919 memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value));
923 void Simulator::set_d_register(int dreg, const uint64_t* value)
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_arm_toIR.c | 693 /* Plain ("low level") read from a VFP Dreg. */
700 /* Architected read from a VFP Dreg. */
705 /* Plain ("low level") write to a VFP Dreg. */
713 /* Architected write to a VFP Dreg. Handles conditional writes to the
736 /* Plain ("low level") read from a Neon Integer Dreg. */
743 /* Architected read from a Neon Integer Dreg. */
748 /* Plain ("low level") write to a Neon Integer Dreg. */
756 /* Architected write to a Neon Integer Dreg. Handles conditional
2859 UInt dreg = get_neon_d_regno(theInstr); local
2908 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
2988 UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); local
3042 UInt dreg = get_neon_d_regno(theInstr); local
4832 UInt dreg = get_neon_d_regno(theInstr); local
5245 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
5911 UInt dreg = get_neon_d_regno(theInstr); local
6626 UInt dreg = get_neon_d_regno(theInstr); local
7646 UInt dreg = get_neon_d_regno(theInstr); local
[all...] |
| host_arm_isel.c | 3736 HReg dreg = iselNeon64Expr(env, triop->arg1); local
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| simulator-arm64.cc | 175 return dreg(0);
618 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1));
619 int64_t result = target(dreg(0), dreg(1));
633 TraceSim("Argument: %f\n", dreg(0));
634 double result = target(dreg(0));
648 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1));
649 double result = target(dreg(0), dreg(1))
[all...] |
| simulator-arm64.h | 427 double dreg(unsigned code) const {
438 case kDRegSizeInBits: return dreg(code);
|
| /external/chromium_org/v8/test/cctest/ |
| test-utils-arm64.h | 89 inline double dreg(unsigned code) const { function in class:RegisterDump
|
| test-utils-arm64.cc | 142 return EqualFP64(expected, core, core->dreg(fpreg.code()));
|
| /external/vixl/test/ |
| test-utils-a64.h | 92 inline double dreg(unsigned code) const { function in class:vixl::RegisterDump
|
| test-utils-a64.cc | 142 return EqualFP64(expected, core, core->dreg(fpreg.code()));
|
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 221 Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0); local
227 EXPECT_TRUE(reg.Overlaps(dreg));
233 dreg = Arm64ManagedRegister::FromDRegister(D5);
239 EXPECT_TRUE(reg.Overlaps(dreg));
245 dreg = Arm64ManagedRegister::FromDRegister(D7);
251 EXPECT_TRUE(reg.Overlaps(dreg));
257 dreg = Arm64ManagedRegister::FromDRegister(D31);
263 EXPECT_TRUE(reg.Overlaps(dreg));
[all...] |
| /external/vixl/test/examples/ |
| test-examples.cc | 224 assert(regs.dreg(0) == Add3DoubleC(A, B, C)); \
250 assert(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
|
| /external/chromium_org/v8/src/mips/ |
| simulator-mips.h | 161 void set_dw_register(int dreg, const int* dbl);
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Blur.S | 103 .irp dreg, 6, 5, 4, 3, 2, 1, 0 ; .irp lane, 3, 2, 1, 0
104 .set i, \dreg * 4 + \lane
121 vmlal.u16 q12, d20, d\dreg[\lane]
123 vmlal.u16 q13, d21, d\dreg[\lane]
125 vmlal.u16 q14, d22, d\dreg[\lane]
127 vmlal.u16 q15, d23, d\dreg[\lane]
[all...] |
| rsCpuIntrinsics_advsimd_Blur.S | 95 .irp dreg, 4, 3, 2, 1, 0 ; .irp lane, 7, 6, 5, 4, 3, 2, 1, 0 ; .irp doth, .h
96 .set i, \dreg * 8 + \lane
106 umlal v12.4s, v16.4h, v\dreg\doth[\lane]
107 umlal2 v13.4s, v16.8h, v\dreg\doth[\lane]
110 umlal v14.4s, v11.4h, v\dreg\doth[\lane]
113 umlal2 v15.4s, v11.8h, v\dreg\doth[\lane]
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_s.h | 625 ;// $dreg = "" don't stack any D registers
632 M_START $name, $rreg, $dreg
651 _M_GETDREGLIST $dreg
711 _M_GETDREGLIST $dreg
712 IF "$dreg"=""
716 IF "$dreg"="d8"
721 IF "$dreg"="d9"
726 IF "$dreg"="d10"
731 IF "$dreg"="d11"
736 IF "$dreg"="d12
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_s.h | 628 ;// $dreg = "" don't stack any D registers
635 M_START $name, $rreg, $dreg
654 _M_GETDREGLIST $dreg
714 _M_GETDREGLIST $dreg
715 IF "$dreg"=""
719 IF "$dreg"="d8"
724 IF "$dreg"="d9"
729 IF "$dreg"="d10"
734 IF "$dreg"="d11"
739 IF "$dreg"="d12
[all...] |
| /external/chromium_org/v8/src/mips64/ |
| simulator-mips64.h | 191 void set_dw_register(int dreg, const int* dbl);
|
