| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 140 #define INT_SRLV dsrlv
185 #define LONG_SRLV dsrlv
240 #define PTR_SRLV dsrlv
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips64.cc | 449 COMPARE(dsrlv(a0, a1, a2),
450 "00c52016 dsrlv a0, a1, a2");
451 COMPARE(dsrlv(s0, s1, s2),
452 "02518016 dsrlv s0, s1, s2");
453 COMPARE(dsrlv(a6, a7, t0),
454 "018b5016 dsrlv a6, a7, t0");
455 COMPARE(dsrlv(v0, v1, fp),
456 "03c31016 dsrlv v0, v1, fp");
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 77 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
80 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 79 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
82 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 79 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
82 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 84 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
87 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 92 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
95 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 40 dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 43 dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 42 dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 44 dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 45 dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/src/mips64/ |
| disasm-mips64.cc | 740 case DSRLV:
742 Format(instr, "dsrlv 'rd, 'rt, 'rs");
[all...] |
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memcpy.S | 115 #define SRLV dsrlv
|
