| /external/compiler-rt/lib/builtins/ppc/ |
| restFP.S | 33 lfd f24,-64(r1)
|
| saveFP.S | 31 stfd f24,-64(r1)
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| fpregdef.h | 54 #define fs2 $f24
97 #define fs0 $f24
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| _setjmp.S | 100 FPREG64_S($f24, JB_F24, a0)
113 swc1 $f24, JB_F24(a0)
157 FPREG64_L($f24, JB_F24, a0)
170 lwc1 $f24, JB_F24(a0)
|
| setjmp.S | 113 FPREG64_S($f24, JB_F24, a0)
126 swc1 $f24, JB_F24(a0)
187 FPREG64_L($f24, JB_F24, a0)
200 lwc1 $f24, JB_F24(a0)
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 8 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/ARM/ |
| symbol-variants.s | 82 .word f24(TLSDESC)
84 @ CHECK: 60 R_ARM_TLS_GOTDESC f24
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32r2.s | 15 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 18 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 10 add.s $f8,$f21,$f24
39 cvt.l.d $f24,$f15
44 cvt.w.s $f20,$f24
84 mfhc1 $s8,$f24
128 nmsub.s $f1,$f24,$f19,$f4
|
| /external/clang/test/CodeGen/ |
| arm-arguments.c | 126 // APCS-GNU-LABEL: define i64 @f24()
132 // AAPCS: define arm_aapcscc void @f24({{.*}} noalias sret
138 _Complex int f24(void) {} function
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 24 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/openssl/crypto/ |
| alphacpuid.pl | 57 fclr $f24
|
| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 79 s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
123 l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
|
