| /external/llvm/test/MC/Mips/ |
| mips64eb-fixups.s | 3 .section .fixups,"",@progbits
27 # CHECK: Name: .fixups (12)
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/ |
| nv50_program.h | 95 void *fixups; /* relocation records */ member in struct:nv50_program
|
| nv50_program.c | 351 prog->fixups = info->bin.relocData;
409 if (prog->fixups)
410 nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0);
434 if (p->fixups)
435 FREE(p->fixups);
|
| /external/mesa3d/src/gallium/drivers/nv50/ |
| nv50_program.h | 95 void *fixups; /* relocation records */ member in struct:nv50_program
|
| nv50_program.c | 351 prog->fixups = info->bin.relocData;
409 if (prog->fixups)
410 nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0);
434 if (p->fixups)
435 FREE(p->fixups);
|
| /external/llvm/test/MC/ARM/ |
| arm-memory-instructions.s | 32 @ to the use of non-contiguous bit ranges for fixups in ARM. Once that's
|
| elf-movt.s | 17 @@ make sure that the text section fixups are sane too
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-fixup-apply.s | 7 # This checks that fixups that can be resolved within the same
|
| ppc64-fixups.s | [all...] |
| /external/llvm/test/MC/Mips/mips32r6/ |
| relocations.s | 6 # Check that the assembler can handle the documented syntax for fixups.
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| relocations.s | 6 # Check that the assembler can handle the documented syntax for fixups.
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/logging/ |
| config.py | 141 fixups = [] #for inter-handler references
168 fixups.append((h, target))
171 for h, t in fixups:
[all...] |
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/logging/ |
| config.py | 141 fixups = [] #for inter-handler references
168 fixups.append((h, target))
171 for h, t in fixups:
[all...] |
| /external/valgrind/main/VEX/priv/ |
| ir_opt.c | 2702 Int fixups[N_FIXUPS]; \/* indices in the stmt array of 'out' *\/ local
[all...] |
