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  /external/llvm/include/llvm/CodeGen/
LivePhysRegs.h 56 LiveRegs.setUniverse(TRI->getNumRegs());
64 LiveRegs.setUniverse(TRI->getNumRegs());
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
SIRegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
R600RegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
  /external/mesa3d/src/gallium/drivers/radeon/
SIRegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
R600RegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
  /external/llvm/lib/CodeGen/
RegisterClassInfo.cpp 56 CSRNum.resize(TRI->getNumRegs(), 0);
83 unsigned NumRegs = RC->getNumRegs();
176 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
CriticalAntiDepBreaker.cpp 37 Classes(TRI->getNumRegs(), nullptr),
38 KillIndices(TRI->getNumRegs(), 0),
39 DefIndices(TRI->getNumRegs(), 0),
40 KeepRegs(TRI->getNumRegs(), false) {}
47 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
108 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
256 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
475 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
529 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
MachineRegisterInfo.cpp 30 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
34 new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
36 sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
62 if (NewRC->getNumRegs() < MinNumRegs)
167 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
402 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
StackMapLivenessAnalysis.cpp 122 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs());
TargetRegisterInfo.cpp 43 else if (TRI && Reg < TRI->getNumRegs())
140 BitVector Allocatable(getNumRegs());
RegisterScavenging.cpp 78 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
88 NumPhysRegs = TRI->getNumRegs();
273 BitVector Mask(TRI->getNumRegs());
ExecutionDepsFix.cpp 157 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
719 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
739 AliasMap.resize(TRI->getNumRegs(), -1);
740 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
InterferenceCache.cpp 35 if (PhysRegEntriesCount == TRI->getNumRegs()) return;
37 PhysRegEntriesCount = TRI->getNumRegs();
AggressiveAntiDepBreaker.cpp 149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
505 BitVector BV(TRI->getNumRegs(), false);
756 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
    [all...]
CallingConvLower.cpp 36 UsedRegs.resize((TRI.getNumRegs()+31)/32);
  /external/llvm/lib/Target/R600/
SIRegisterInfo.cpp 27 BitVector Reserved(getNumRegs());
37 return RC->getNumRegs();
R600RegisterInfo.cpp 28 BitVector Reserved(getNumRegs());
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.cpp 88 BitVector Reserved(getNumRegs());
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 58 /// getNumRegs - Return the number of registers in this class.
60 unsigned getNumRegs() const { return RegsSize; }
65 assert(i < getNumRegs() && "Register number out of range!");
359 unsigned getNumRegs() const {
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 64 /// getNumRegs - Return the number of registers in this class.
66 unsigned getNumRegs() const { return MC->getNumRegs(); }
195 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
431 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
    [all...]
  /external/llvm/lib/MC/
MCRegisterInfo.cpp 39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
  /external/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 289 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
290 Uses(TRI.getNumRegs(), false) {}
313 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
349 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 37 BitVector Reserved(getNumRegs());
  /external/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 414 ModifiedRegs.resize(TRI->getNumRegs());
415 UsedRegs.resize(TRI->getNumRegs());
665 ModifiedRegs.resize(TRI->getNumRegs());
666 UsedRegs.resize(TRI->getNumRegs());
718 ModifiedRegs.resize(TRI->getNumRegs());
719 UsedRegs.resize(TRI->getNumRegs());
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonCallingConvLower.cpp 34 UsedRegs.resize((TM.getRegisterInfo()->getNumRegs()+31)/32);

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