/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600ExpandSpecialInstrs.cpp | 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); 107 Src1 = TRI.getSubReg(Src1, SubRegIndex); 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
|
/external/mesa3d/src/gallium/drivers/radeon/ |
R600ExpandSpecialInstrs.cpp | 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); 107 Src1 = TRI.getSubReg(Src1, SubRegIndex); 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
|
/external/llvm/lib/CodeGen/ |
CalcSpillWeights.cpp | 49 sub = mi->getOperand(0).getSubReg(); 51 hsub = mi->getOperand(1).getSubReg(); 53 sub = mi->getOperand(1).getSubReg(); 55 hsub = mi->getOperand(0).getSubReg();
|
TargetRegisterInfo.cpp | 193 if (RCI.getSubReg() == Idx) 232 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 241 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 251 *BestPreA = IA.getSubReg(); 252 *BestPreB = IB.getSubReg();
|
PeepholeOptimizer.cpp | 316 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) 544 unsigned DefSubReg = MODef.getSubReg(); 614 if (!MI->getOperand(0).getSubReg() && 791 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) 797 SrcSubReg = Def->getOperand(SrcIdx).getSubReg(); 812 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) 829 SrcSubReg = Def->getOperand(SrcIdx).getSubReg(); 837 if (Def->getOperand(DefIdx).getSubReg()) [all...] |
OptimizePHIs.cpp | 110 !SrcMI->getOperand(0).getSubReg() && 111 !SrcMI->getOperand(1).getSubReg() &&
|
RegisterCoalescer.cpp | 221 DstSub = MI->getOperand(0).getSubReg(); 223 SrcSub = MI->getOperand(1).getSubReg(); 226 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), 229 SrcSub = MI->getOperand(2).getSubReg(); 276 Dst = TRI.getSubReg(Dst, DstSub); 370 Dst = TRI.getSubReg(Dst, DstSub); 375 return TRI.getSubReg(DstReg, SrcSub) == Dst; 694 UseMI->getOperand(0).getSubReg()) 767 if (DstOperand.getSubReg() && !DstOperand.isUndef()) 784 DefMI->getOperand(0).getSubReg()); [all...] |
ExpandPostRAPseudos.cpp | 88 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 92 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
|
RegAllocFast.cpp | 670 if (!MO.getSubReg()) { 676 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); 707 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 745 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { [all...] |
MachineInstr.cpp | 71 if (SubIdx && getSubReg()) 72 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 80 if (getSubReg()) { 81 Reg = TRI.getSubReg(Reg, getSubReg()); 82 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 177 getSubReg() == Other.getSubReg(); 219 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 272 OS << PrintReg(getReg(), TRI, getSubReg()); [all...] |
TargetInstrInfo.cpp | 139 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; 140 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); 141 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg(); 351 if (FoldOp.getSubReg() || LiveOp.getSubReg()) 423 bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, 578 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
|
VirtRegMap.cpp | 345 if (MO.getSubReg()) { 367 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
|
/external/llvm/lib/Target/R600/ |
SIFixSGPRCopies.cpp | 151 I->getOperand(0).getSubReg())); 174 Def->getOperand(1).getSubReg()); 183 unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); 225 MI.getOperand(0).getSubReg()); 230 MI.getOperand(0).getSubReg());
|
R600ExpandSpecialInstrs.cpp | 186 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); 286 Src0 = TRI.getSubReg(Src0, SubRegIndex); 287 Src1 = TRI.getSubReg(Src1, SubRegIndex); 292 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 293 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 301 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
|
/external/llvm/lib/MC/ |
MCRegisterInfo.cpp | 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) 26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
|
/external/llvm/lib/Target/Sparc/ |
SparcRegisterInfo.cpp | 179 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); 180 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); 191 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); 192 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
|
/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 140 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), 142 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) 144 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), 146 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), 148 SubReg = MI->getOperand(1).getSubReg();
|
/external/llvm/lib/Target/Hexagon/ |
HexagonSplitConst32AndConst64.cpp | 142 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg); 144 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
|
HexagonHardwareLoops.cpp | 259 unsigned getSubReg() const { 761 SR = Start->getSubReg(); 764 SR = End->getSubReg(); 779 DistSR = End->getSubReg(); 789 SubIB.addReg(End->getReg(), 0, End->getSubReg()) 790 .addReg(Start->getReg(), 0, Start->getSubReg()); 793 .addReg(Start->getReg(), 0, Start->getSubReg()); 795 SubIB.addReg(End->getReg(), 0, End->getSubReg()) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMMCInstLower.cpp | 76 assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
Thumb2ITBlockPass.cpp | 115 assert(MI->getOperand(0).getSubReg() == 0 && 116 MI->getOperand(1).getSubReg() == 0 &&
|
ARMExpandPseudoInsts.cpp | 360 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 361 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 362 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 363 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 365 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 366 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 367 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 368 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 371 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 372 D1 = TRI->getSubReg(Reg, ARM::dsub_3) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 566 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 588 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
|
/external/llvm/lib/Target/SystemZ/ |
SystemZElimCompare.cpp | 114 MI->getOperand(0).getSubReg() == SubReg) 131 MI->getOperand(1).getSubReg() == SubReg) 329 unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
|
/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 727 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 742 getOperand(0).getSubReg() == getOperand(1).getSubReg(); [all...] |