| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 173 Entry.isSExt = false;
185 Entry.isSExt = true;
|
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 66 bool isSExt() const { return Flags & SExt; }
|
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 723 bool isSExt = true;
726 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
728 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
730 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
732 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
734 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
736 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
738 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
740 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
746 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeTypes.cpp | [all...] |
| TargetLowering.cpp | 72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
99 Entry.isSExt = isSigned;
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 123 if (ArgFlags.isSExt())
161 if (ArgFlags.isSExt())
236 if (ArgFlags.isSExt())
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 310 if (ArgFlags.isSExt())
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 407 Ins[i].Flags.isSExt());
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
