/external/llvm/test/MC/Mips/ |
micromips-loadstore-unaligned.s | 12 # CHECK-EL: lwl $4, 16($5) # encoding: [0x85,0x60,0x10,0x00] 19 # CHECK-EB: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10] 23 lwl $4, 16($5)
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/external/chromium_org/v8/src/mips/ |
codegen-mips.cc | 143 __ lwl(t8, MemOperand(a1)); 301 __ lwl(v1, 307 __ lwl(v1, MemOperand(a1)); 361 __ lwl(t0, 363 __ lwl(t1, 365 __ lwl(t2, 367 __ lwl(t3, 369 __ lwl(t4, 371 __ lwl(t5, 373 __ lwl(t6 [all...] |
/external/llvm/test/MC/Mips/mips32r6/ |
invalid-mips1-wrong-error.s | 10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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/external/llvm/test/MC/Mips/mips64r6/ |
invalid-mips1-wrong-error.s | 10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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invalid-mips3-wrong-error.s | 16 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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/external/openssl/crypto/sha/asm/ |
sha1-mips.S | 39 lwl $8,3($5) 52 lwl $9,1*4+3($5) 76 lwl $10,2*4+3($5) 100 lwl $11,3*4+3($5) 124 lwl $12,4*4+3($5) 148 lwl $13,5*4+3($5) 172 lwl $14,6*4+3($5) 196 lwl $15,7*4+3($5) 220 lwl $16,8*4+3($5) 244 lwl $17,9*4+3($5 [all...] |
sha256-mips.S | 49 lwl $8,3($5) 51 lwl $9,7($5) 103 lwl $10,11($5) 155 lwl $11,15($5) 207 lwl $12,19($5) 259 lwl $13,23($5) 311 lwl $14,27($5) 363 lwl $15,31($5) 415 lwl $16,35($5) 467 lwl $17,39($5 [all...] |
/external/openssl/crypto/aes/asm/ |
aes-mips.S | 41 lwl $12,2($1) # Te1[s1>>16] 42 lwl $13,2($2) # Te1[s2>>16] 43 lwl $14,2($24) # Te1[s3>>16] 44 lwl $15,2($25) # Te1[s0>>16] 62 lwl $16,1($1) # Te2[s2>>8] 63 lwl $17,1($2) # Te2[s3>>8] 64 lwl $18,1($24) # Te2[s0>>8] 65 lwl $19,1($25) # Te2[s1>>8] 83 lwl $20,0($1) # Te3[s3] 84 lwl $21,0($2) # Te3[s0 [all...] |
aes-mips.pl | 18 # additional rotations. Rotations are implemented with lwl/lwr pairs, 142 lwl $t0,3($i0) # Te1[s1>>16] 143 lwl $t1,3($i1) # Te1[s2>>16] 144 lwl $t2,3($i2) # Te1[s3>>16] 145 lwl $t3,3($i3) # Te1[s0>>16] 163 lwl $t4,2($i0) # Te2[s2>>8] 164 lwl $t5,2($i1) # Te2[s3>>8] 165 lwl $t6,2($i2) # Te2[s0>>8] 166 lwl $t7,2($i3) # Te2[s1>>8] 184 lwl $t8,1($i0) # Te3[s3 [all...] |
/external/chromium_org/v8/src/mips64/ |
codegen-mips64.cc | 301 __ lwl(v1, 352 __ lwl(a4, 354 __ lwl(a5, 356 __ lwl(a6, 358 __ lwl(a7, 360 __ lwl(t0, 362 __ lwl(t1, 364 __ lwl(t2, 366 __ lwl(t3, 385 __ lwl(a4 [all...] |
/bionic/libc/arch-mips/include/machine/ |
asm.h | 65 #define LWLO lwl 76 #define LWHI lwl
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/bionic/libc/arch-mips64/include/machine/ |
asm.h | 65 #define LWLO lwl 76 #define LWHI lwl
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/development/ndk/platforms/android-L/arch-mips/include/machine/ |
asm.h | 65 #define LWLO lwl 76 #define LWHI lwl
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/development/ndk/platforms/android-L/arch-mips64/include/machine/ |
asm.h | 65 #define LWLO lwl 76 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-21/arch-mips/usr/include/machine/ |
asm.h | 65 #define LWLO lwl 76 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-21/arch-mips64/usr/include/machine/ |
asm.h | 65 #define LWLO lwl 76 #define LWHI lwl
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/development/ndk/platforms/android-9/arch-mips/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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/prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/machine/ |
asm.h | 68 #define LWLO lwl 79 #define LWHI lwl
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