| /external/qemu/ |
| cputlb.c | 59 int mmu_idx; local
61 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
62 env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
88 int mmu_idx; local
109 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
110 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr)
164 int mmu_idx; local
305 int mmu_idx, page_index, pd; local
[all...] |
| exec.c | 561 int mmu_idx; local
562 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
565 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
615 int mmu_idx; local
616 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
618 tlb_update_dirty(&env->tlb_table[mmu_idx][i])
[all...] |
| /external/qemu/include/exec/ |
| softmmu_template.h | 147 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
151 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
163 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
166 tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
167 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
176 ioaddr = env->iotlb[mmu_idx][index];
194 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
200 res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
201 res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
212 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr)
[all...] |
| softmmu_header.h | 89 int mmu_idx; local
93 mmu_idx = CPU_MMU_INDEX;
94 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
96 res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
98 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
110 int mmu_idx; local
114 mmu_idx = CPU_MMU_INDEX;
115 if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
118 MMUSUFFIX)(env, addr, mmu_idx);
120 uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend
137 int mmu_idx; local
[all...] |
| exec-all.h | 107 int mmu_idx, target_ulong size);
361 void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
364 uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
365 uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
366 uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
367 uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
|
| /external/qemu/tcg/ |
| tcg.h | 777 int mmu_idx, uintptr_t retaddr);
779 int mmu_idx, uintptr_t retaddr);
781 int mmu_idx, uintptr_t retaddr);
783 int mmu_idx, uintptr_t retaddr);
785 int mmu_idx, uintptr_t retaddr);
787 int mmu_idx, uintptr_t retaddr);
789 int mmu_idx, uintptr_t retaddr);
793 int mmu_idx, uintptr_t retaddr);
795 int mmu_idx, uintptr_t retaddr);
797 int mmu_idx, uintptr_t retaddr)
[all...] |
| /external/qemu/target-i386/ |
| mem_helper.c | 132 void tlb_fill(CPUX86State* env, target_ulong addr, int is_write, int mmu_idx,
137 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx);
|
| helper.c | [all...] |
| cpu.h | 960 int is_write, int mmu_idx);
[all...] |
| /external/qemu/target-mips/ |
| helper.c | 346 int mmu_idx, int is_softmmu)
424 mmu_idx, TARGET_PAGE_SIZE);
439 int mmu_idx)
452 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
453 __func__, env->active_tc.PC, address, rw, mmu_idx);
471 mmu_idx, TARGET_PAGE_SIZE);
475 ret = cpu_mips_tlb_refill(env,address,rw,mmu_idx,1);
|
| cpu.h | 431 the bits as the value of mmu_idx. */
653 int mmu_idx);
|
| op_helper.c | [all...] |
| /external/qemu/target-arm/ |
| op_helper.c | 78 void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
83 ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
|
| cpu.h | 307 int mmu_idx);
|
| helper.c | 628 int mmu_idx)
[all...] |
