| /external/llvm/test/MC/AArch64/ |
| elf-reloc-movw.s | 17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
|
| tls-relocs.s | 7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
13 // CHECK: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92]
17 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
35 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
39 // CHECK: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:va
[all...] |
| arm64-tls-relocs.s | 44 movn x4, #:tprel_g2:var
47 // CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
55 movn x6, #:tprel_g1:var
59 // CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
81 movn x12, #:tprel_g0:var
85 // CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
168 movn x4, #:dtprel_g2:var
171 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
179 movn x6, #:dtprel_g1:var
183 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-movcond-instructions.s | 13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
|
| micromips-fpu-instructions.s | 58 # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
59 # CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
121 # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
122 # CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
180 movn.s $f4, $f6, $7
181 movn.d $f4, $f6, $7
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 18 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 19 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 15 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.stdout.exp | 192 MOVN.S
193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db000
[all...] |
| /frameworks/native/opengl/libagl/arch-mips/ |
| fixed_asm.S | 50 movn $v0,$t2,$t0 /* if negative? */
|
| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 79 DBG movn $v0,$t8,$at
81 DBG movn $v1,$t8,$at
166 DBG movn $v0,$t8,$at
168 DBG movn $v1,$t8,$at
|
| /external/libhevc/common/arm64/ |
| ihevc_sao_edge_offset_class2_chroma.s | 142 movn x20,#0
150 movn x20,#0
178 movn x20,#0
185 movn x20,#0
224 movn x20,#0
234 movn x20,#0
260 movn x20,#0
270 movn x20,#0
427 movn x20,#0
434 movn x20,#
[all...] |
| ihevc_sao_edge_offset_class3_chroma.s | 137 movn x20,#0
146 movn x20,#0
170 movn x20,#0
179 movn x20,#0
216 movn x20,#0
225 movn x20,#0
251 movn x20,#0
260 movn x20,#0
411 movn x20,#0
419 movn x20,#
[all...] |
| ihevc_sao_edge_offset_class2.s | 125 movn x20,#0
134 movn x20,#0
169 movn x20,#0
175 movn x20,#0
306 movn x20,#0
380 movn x20,#0
394 movn x20,#0
484 movn x20,#0
[all...] |
| ihevc_sao_edge_offset_class3.s | 130 movn x20,#0
137 movn x20,#0
176 movn x20,#0
182 movn x20,#0
319 movn x20,#0
383 movn x20,#0
413 movn x20,#0
514 movn x20,#0
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 28 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips32r2.s | 35 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
37 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 57 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
58 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 56 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
58 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips64.s | 29 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 467 COMPARE(movn(a0, a1, a2),
468 "00a6200b movn a0, a1, a2");
469 COMPARE(movn(s0, s1, s2),
470 "0232800b movn s0, s1, s2");
471 COMPARE(movn(t2, t3, t4),
472 "016c500b movn t2, t3, t4");
473 COMPARE(movn(v0, v1, a2),
474 "0066100b movn v0, v1, a2");
|
| test-disasm-mips64.cc | 618 COMPARE(movn(a0, a1, a2),
619 "00a6200b movn a0, a1, a2");
620 COMPARE(movn(s0, s1, s2),
621 "0232800b movn s0, s1, s2");
622 COMPARE(movn(a6, a7, t0),
623 "016c500b movn a6, a7, t0");
624 COMPARE(movn(v0, v1, a2),
625 "0066100b movn v0, v1, a2");
|
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_luma_dc.s | 235 vqshrun.s16 d2, q10, #2 @columns shr2 movn (prol)
241 vqshrun.s16 d3, q11, #2 @rows shr2 movn (prol)
261 vqshrun.s16 d4, q13, #2 @columns shr2 movn (prol extra)
319 vqshrun.s16 d3, q11, #2 @rows shr2 movn (prol)
469 vqshrun.s16 d2, q10, #2 @columns shr2 movn (prol)
472 vqshrun.s16 d3, q11, #2 @rows shr2 movn (prol)
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 82 movn $v1,$s1,$s0
83 movn.d $f27,$f21,$k0
84 movn.s $f12,$f0,$s7
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 95 movn $v1,$s1,$s0
96 movn.d $f27,$f21,$k0
97 movn.s $f12,$f0,$s7
|
