| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 65 MI->getOperand(0).setReg(NewReg);
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| Spiller.cpp | 124 mop.setReg(NewVReg);
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| MachineRegisterInfo.cpp | 293 O.setReg(ToReg);
427 nextI = std::next(I); // I is invalidated by the setReg
430 UseMI->getOperand(0).setReg(0U);
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| TailDuplication.cpp | 443 MO.setReg(NewReg);
450 MO.setReg(VI->second);
516 II->getOperand(Idx).setReg(SrcReg);
528 II->getOperand(Idx).setReg(Reg);
[all...] |
| TargetInstrInfo.cpp | 165 MI->getOperand(0).setReg(Reg0);
168 MI->getOperand(Idx2).setReg(Reg1);
169 MI->getOperand(Idx1).setReg(Reg2);
229 MO.setReg(Pred[j].getReg());
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| MachineSSAUpdater.cpp | 232 U.setReg(NewVR);
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| RegAllocFast.cpp | 671 MO.setReg(PhysReg);
676 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
859 MO.setReg(0);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZShortenInst.cpp | 88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 258 MI->getOperand(0).setReg(PeepholeSrc);
296 MI->getOperand(PR).setReg(POrig);
319 Dst.setReg(Src.getReg());
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| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 110 MO.setReg(NewReg);
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| AArch64A57FPLoadBalancing.cpp | 530 U.setReg(Substs[OrigReg]);
556 MO.setReg(Reg);
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| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 382 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
421 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
455 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
456 RestoreMI->getOperand(1).setReg(SP::G0);
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| SparcRegisterInfo.cpp | 186 MI.getOperand(2).setReg(SrcOddReg);
199 MI.getOperand(0).setReg(DestOddReg);
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| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 138 I->getOperand(0).setReg(DstReg);
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
|
| /external/llvm/lib/Target/R600/ |
| R600EmitClauseMarkers.cpp | 164 Consts[i].first->setReg(
168 Consts[i].first->setReg(
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| R600ExpandSpecialInstrs.cpp | 87 DstOp.setReg(AMDGPU::OQAP);
93 Mov->getOperand(MovPredSelIdx).setReg(
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| R600InstrInfo.cpp | 988 MO2.setReg(AMDGPU::PRED_SEL_ONE);
991 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
1025 .setReg(Pred[2].getReg());
1027 .setReg(Pred[2].getReg())
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 427 MO2.setReg(AMDGPU::PRED_SEL_ONE);
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
462 PMO.setReg(Pred[2].getReg());
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 427 MO2.setReg(AMDGPU::PRED_SEL_ONE);
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
462 PMO.setReg(Pred[2].getReg());
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| /external/llvm/include/llvm/MC/ |
| MCInst.h | 68 /// setReg - Set the register number.
69 void setReg(unsigned Reg) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 286 MI->getOperand(0).setReg(Reg2);
289 MI->getOperand(2).setReg(Reg1);
290 MI->getOperand(1).setReg(Reg2);
[all...] |
| /external/libcxxabi/src/Unwind/ |
| UnwindCursor.hpp | 373 virtual void setReg(int, unw_word_t) = 0;
401 virtual void setReg(int, unw_word_t);
564 void UnwindCursor<A, R>::setReg(int regNum, unw_word_t value) {
[all...] |
| libunwind.cpp | 176 co->setReg(regNum, (pint_t)value);
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| /ndk/sources/cxx-stl/llvm-libc++abi/libcxxabi/src/Unwind/ |
| UnwindCursor.hpp | 373 virtual void setReg(int, unw_word_t) = 0;
401 virtual void setReg(int, unw_word_t);
564 void UnwindCursor<A, R>::setReg(int regNum, unw_word_t value) {
[all...] |
| libunwind.cpp | 176 co->setReg(regNum, (pint_t)value);
|
