| /external/clang/test/CodeGen/ |
| ppc64-vector.c | 5 typedef short v4i16 __attribute__((vector_size (8))); typedef
25 v4i16 test_v4i16(v4i16 x)
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 215 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
216 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
220 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
223 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
224 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
267 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
268 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
484 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2}
[all...] |
| ARMISelLowering.cpp | 427 addDRTypeForNEON(MVT::v4i16);
517 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
519 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
527 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
528 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
529 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
530 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
540 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
567 // It is legal to extload from v4i8 to v4i16 or v4i32.
569 MVT::v4i16, MVT::v2i16
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 74 v4i16 = 28, // 4 x i16 enumerator in enum:llvm::MVT::SimpleValueType
204 return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 ||
283 case v4i16:
337 case v4i16:
399 case v4i16:
529 if (NumElements == 4) return MVT::v4i16;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 458 case MVT::v4i16:
[all...] |
| AArch64TargetTransformInfo.cpp | 325 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
327 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
354 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
355 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
357 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
|
| AArch64ISelLowering.cpp | 105 addDRTypeForNEON(MVT::v4i16);
427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
616 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 581 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
582 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
587 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
608 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
609 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
614 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
627 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
631 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
640 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
644 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 146 case MVT::v4i16: return "v4i16";
214 case MVT::v4i16: return VectorType::get(Type::getInt16Ty(Context), 4);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 60 (int)MVT::v4i16,
88 (int)MVT::v4i16,
210 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
668 } else if (OVT == MVT::v4i16) {
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 60 (int)MVT::v4i16,
88 (int)MVT::v4i16,
210 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
668 } else if (OVT == MVT::v4i16) {
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 87 case MVT::v4i16: return "MVT::v4i16";
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 173 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
226 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
227 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
228 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
[all...] |
| SIISelLowering.cpp | 127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
[all...] |
| R600ISelLowering.cpp | 106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 60 case MVT::v4i16:
[all...] |
