| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_3DLUT.S | 23 .macro lanepair dst, src, xr0, xr1, yr0, yr1, zr0, zr1
87 vmlsl.u16 q9, d22, \xr1
89 vmlal.u16 q9, d23, \xr1
189 lanepair dst=d12, src=d12, xr0=d0[0], xr1=d0[1], yr0=d2[0], yr1=d2[1], zr0=d4[0], zr1=d4[1]
192 lanepair dst=d13, src=d13, xr0=d0[2], xr1=d0[3], yr0=d2[2], yr1=d2[3], zr0=d4[2], zr1=d4[3]
195 lanepair dst=d14, src=d14, xr0=d1[0], xr1=d1[1], yr0=d2[4], yr1=d2[5], zr0=d5[0], zr1=d5[1]
198 lanepair dst=d15, src=d15, xr0=d1[2], xr1=d1[3], yr0=d2[6], yr1=d2[7], zr0=d5[2], zr1=d5[3]
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| rsCpuIntrinsics_advsimd_3DLUT.S | 21 .macro lanepair dst, src0, src1, xr0, xr1, yr0, yr1, zr0, zr1
86 umlsl v9.4s, v11.4h, \xr1
88 umlal2 v9.4s, v11.8h, \xr1
189 lanepair dst=v20.8b, src0=v6.s[0], src1=v6.s[1], xr0=v0.h[0], xr1=v0.h[1], yr0=v1.b[0], yr1=v1.b[1], zr0=v2.h[0], zr1=v2.h[1]
192 lanepair dst=v20.16b, src0=v6.s[2], src1=v6.s[3], xr0=v0.h[2], xr1=v0.h[3], yr0=v1.b[2], yr1=v1.b[3], zr0=v2.h[2], zr1=v2.h[3]
195 lanepair dst=v21.8b, src0=v7.s[0], src1=v7.s[1], xr0=v0.h[4], xr1=v0.h[5], yr0=v1.b[4], yr1=v1.b[5], zr0=v2.h[4], zr1=v2.h[5]
198 lanepair dst=v21.16b, src0=v7.s[2], src1=v7.s[3], xr0=v0.h[6], xr1=v0.h[7], yr0=v1.b[6], yr1=v1.b[7], zr0=v2.h[6], zr1=v2.h[7]
|
| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 201 xr1 = RegStorage::k128BitSolo | 1, enumerator in enum:art::X86NativeRegisterPool
297 constexpr RegStorage rs_xr1(RegStorage::kValid | xr1);
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| wingdi.h | [all...] |
