| /external/llvm/test/CodeGen/PowerPC/ |
| vperm-lowering.ll | 11 ; CHECK: .LCPI0_0:
12 ; CHECK: .byte 31
13 ; CHECK: .byte 26
14 ; CHECK: .byte 21
15 ; CHECK: .byte 16
16 ; CHECK: .byte 11
17 ; CHECK: .byte 6
18 ; CHECK: .byte 1
19 ; CHECK: .byte 28
20 ; CHECK: .byte 2
[all...] |
| /external/llvm/test/MC/ELF/ |
| empty-dwarf-lines.s | 10 // CHECK: Section {
11 // CHECK: Index: 4
12 // CHECK-NEXT: Name: .debug_line
13 // CHECK-NEXT: Type: SHT_PROGBITS
14 // CHECK-NEXT: Flags [
15 // CHECK-NEXT: ]
16 // CHECK-NEXT: Address: 0x0
17 // CHECK-NEXT: Offset: 0x44
18 // CHECK-NEXT: Size: 39
19 // CHECK-NEXT: Link:
[all...] |
| pic-diff.s | 3 // CHECK: Relocations [
4 // CHECK-NEXT: Section ({{[^ ]+}}) {{[^ ]+}} {
5 // CHECK-NEXT: 0xC R_X86_64_PC32 baz 0x8
6 // CHECK-NEXT: }
7 // CHECK-NEXT: ]
9 // CHECK: Symbol {
10 // CHECK: Name: baz
11 // CHECK-NEXT: Value: 0x0
12 // CHECK-NEXT: Size: 0
13 // CHECK-NEXT: Binding: Globa
[all...] |
| /external/llvm/test/MC/MachO/ARM/ |
| static-movt-relocs.s | 10 @ CHECK: ('_relocations', [
11 @ CHECK: # Relocation 0
12 @ CHECK: (('word-0', 0x4),
13 @ CHECK: ('word-1', 0x8e000001)),
14 @ CHECK: # Relocation 1
15 @ CHECK: (('word-0', 0x10),
16 @ CHECK: ('word-1', 0x16ffffff)),
17 @ CHECK: # Relocation 2
18 @ CHECK: (('word-0', 0x0),
19 @ CHECK: ('word-1', 0x8c000001))
[all...] |
| /external/llvm/test/MC/Mips/ |
| mips-bad-branches.s | 3 # CHECK: error: branch to misaligned address
4 # CHECK: b -131069
5 # CHECK: error: branch to misaligned address
6 # CHECK: b -131070
7 # CHECK: error: branch to misaligned address
8 # CHECK: b -131071
9 # CHECK: error: branch target out of range
10 # CHECK: b -131073
11 # CHECK: error: branch to misaligned address
12 # CHECK: b 13106
[all...] |
| /external/llvm/test/MC/AArch64/ |
| trace-regs-diagnostics.s | 5 // CHECK: error: expected readable system register
6 // CHECK-NEXT: mrs x12, trcoslar
7 // CHECK-NEXT: ^
8 // CHECK-NEXT: error: expected readable system register
9 // CHECK-NEXT: mrs x10, trclar
10 // CHECK-NEXT: ^
49 // CHECK: error: expected writable system register or pstate
50 // CHECK-NEXT: msr trcstatr, x0
51 // CHECK-NEXT: ^
52 // CHECK-NEXT: error: expected writable system register or pstat
[all...] |
| /external/llvm/test/MC/X86/ |
| x86-16.s | 4 // CHECK: movl
5 // CHECK: encoding: [0x66,0xbb,0x78,0x56,0x34,0x12]
7 // CHECK: pause
8 // CHECK: encoding: [0xf3,0x90]
10 // CHECK: sfence
11 // CHECK: encoding: [0x0f,0xae,0xf8]
13 // CHECK: lfence
14 // CHECK: encoding: [0x0f,0xae,0xe8]
17 // CHECK: stgi
18 // CHECK: encoding: [0x0f,0x01,0xdc
[all...] |
| /external/clang/test/Analysis/inlining/ |
| eager-reclamation-path-notes.cpp | 37 // CHECK: <key>diagnostics</key>
38 // CHECK-NEXT: <array>
39 // CHECK-NEXT: <dict>
40 // CHECK-NEXT: <key>path</key>
41 // CHECK-NEXT: <array>
42 // CHECK-NEXT: <dict>
43 // CHECK-NEXT: <key>kind</key><string>control</string>
44 // CHECK-NEXT: <key>edges</key>
45 // CHECK-NEXT: <array>
46 // CHECK-NEXT: <dict
[all...] |
| /external/clang/test/Layout/ |
| ms-x86-basic-layout.cpp | 4 // RUN: | FileCheck %s -check-prefix CHECK-X64
40 // CHECK: *** Dumping AST Record Layout
41 // CHECK: *** Dumping AST Record Layout
42 // CHECK: *** Dumping AST Record Layout
43 // CHECK-NEXT: 0 | struct TestF0
44 // CHECK-NEXT: 0 | struct A4 (base)
45 // CHECK-NEXT: 0 | int a
46 // CHECK-NEXT: 4 | (TestF0 vbtable pointer)
47 // CHECK-NEXT: 8 | int
[all...] |
| ms-x86-lazy-empty-nonvirtual-base.cpp | 4 // RUN: | FileCheck %s -check-prefix CHECK-X64
34 // CHECK: *** Dumping AST Record Layout
35 // CHECK: *** Dumping AST Record Layout
36 // CHECK: *** Dumping AST Record Layout
37 // CHECK: *** Dumping AST Record Layout
38 // CHECK-NEXT: 0 | struct AA
39 // CHECK-NEXT: 0 | struct B8 (base)
40 // CHECK-NEXT: 0 | char [5] c
41 // CHECK-NEXT: 13 | struct B1 (base) (empty
[all...] |
| /external/llvm/test/MC/SystemZ/ |
| insn-bad.s | 5 #CHECK: error: invalid operand
6 #CHECK: a %r0, -1
7 #CHECK: error: invalid operand
8 #CHECK: a %r0, 4096
13 #CHECK: error: invalid operand
14 #CHECK: adb %f0, -1
15 #CHECK: error: invalid operand
16 #CHECK: adb %f0, 4096
21 #CHECK: error: invalid operand
22 #CHECK: aeb %f0, -
[all...] |
| /external/llvm/test/MC/Disassembler/X86/ |
| fp-stack.txt | 4 # CHECK: fadd %st(0)
7 # CHECK: fadd %st(1)
10 # CHECK: fadd %st(2)
13 # CHECK: fadd %st(3)
16 # CHECK: fadd %st(4)
19 # CHECK: fadd %st(5)
22 # CHECK: fadd %st(6)
25 # CHECK: fadd %st(7)
28 # CHECK: fmul %st(0)
31 # CHECK: fmul %st(1
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2014-02-21-byval-reg-split-alignment.ll | 15 ; CHECK-LABEL: foo1
16 ; CHECK: sub sp, sp, #16
17 ; CHECK: push {r11, lr}
18 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #12
19 ; CHECK: stm [[SCRATCH]], {r1, r2, r3}
20 ; CHECK: ldr r0, [sp, #24]
21 ; CHECK: ldr r1, [sp, #28]
22 ; CHECK: bl useLong
23 ; CHECK: pop {r11, lr}
24 ; CHECK: add sp, sp, #1
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| atom-bypass-slow-division.ll | 4 ; CHECK-LABEL: Test_get_quotient:
5 ; CHECK: orl %ecx, %edx
6 ; CHECK-NEXT: testl $-256, %edx
7 ; CHECK-NEXT: je
8 ; CHECK: idivl
9 ; CHECK: ret
10 ; CHECK: divb
11 ; CHECK: ret
17 ; CHECK-LABEL: Test_get_remainder:
18 ; CHECK: orl %ecx, %ed
[all...] |
| bitcast-i256.ll | 1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i < %s | FileCheck %s --check-prefix CHECK
6 ; CHECK: foo
7 ; CHECK: vextractf128
8 ; CHECK: vpextrq
9 ; CHECK: vpextrq
10 ; CHECK: ret
|
| /external/llvm/test/Object/ |
| yaml2obj-elf-rel.yaml | 64 # CHECK: Section {
65 # CHECK-NEXT: Index: 0
66 # CHECK: }
67 # CHECK: Section {
68 # CHECK-NEXT: Index: 1
69 # CHECK-NEXT: Name: .text (16)
70 # CHECK: }
71 # CHECK-NEXT: Section {
72 # CHECK-NEXT: Index: 2
73 # CHECK-NEXT: Name: .rel.text (1
[all...] |
| /external/clang/test/CodeGen/ |
| atomic_ops.c | 7 // Check that multiply / divides on atomics produce a cmpxchg loop
9 // CHECK: mul nsw i32
10 // CHECK: cmpxchg i32*
12 // CHECK: sdiv i32
13 // CHECK: cmpxchg i32*
15 // CHECK: sdiv i32
16 // CHECK: cmpxchg i16*
|
| /external/clang/test/CodeGenCXX/ |
| deferred-global-init.cpp | 8 // CHECK: @_ZL1a = internal global i8* null
10 // CHECK-LABEL: define internal void @__cxx_global_var_init
11 // CHECK: load i8** @foo
12 // CHECK: ret void
14 // CHECK-LABEL: define internal void @_GLOBAL__sub_I_deferred_global_init.cpp
15 // CHECK: call void @__cxx_global_var_init()
16 // CHECK: ret void
|
| /external/clang/test/Preprocessor/ |
| pic.c | 3 // CHECK-NOT: #define __PIC__
4 // CHECK-NOT: #define __PIE__
5 // CHECK-NOT: #define __pic__
6 // CHECK-NOT: #define __pie__
9 // RUN: | FileCheck --check-prefix=CHECK-PIC1 %s
10 // CHECK-PIC1: #define __PIC__ 1
11 // CHECK-PIC1-NOT: #define __PIE__
12 // CHECK-PIC1: #define __pic__ 1
13 // CHECK-PIC1-NOT: #define __pie_
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| frame-address.ll | 10 ; CHECK: .cfi_startproc
11 ; CHECK: .cfi_def_cfa_offset 8
12 ; CHECK: .cfi_offset 30, -4
13 ; CHECK: move $fp, $sp
14 ; CHECK: .cfi_def_cfa_register 30
15 ; CHECK: move $2, $fp
16 ; CHECK: .cfi_endproc
|
| /external/llvm/test/CodeGen/XCore/ |
| varargs.ll | 5 ; CHECK-LABEL: _Z1fz:
6 ; CHECK: extsp 3
7 ; CHECK: stw r[[REG:[0-3]{1,1}]]
8 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
9 ; CHECK: stw r[[REG:[0-3]{1,1}]]
10 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
11 ; CHECK: stw r[[REG:[0-3]{1,1}]]
12 ; CHECK: , sp{{\[}}[[REG]]{{\]}}
13 ; CHECK: stw r[[REG:[0-3]{1,1}]]
14 ; CHECK: , sp{{\[}}[[REG]]{{\]}
[all...] |
| /external/llvm/test/DebugInfo/ |
| dwarfdump-ranges.test | 3 CHECK: .debug_ranges contents:
4 CHECK-NEXT: 00000000 000000000000062c 0000000000000637
5 CHECK-NEXT: 00000000 0000000000000637 000000000000063d
6 CHECK-NEXT: 00000000 <End of list>
7 CHECK-NEXT: 00000030 0000000000000640 000000000000064b
8 CHECK-NEXT: 00000030 0000000000000637 000000000000063d
9 CHECK-NEXT: 00000030 <End of list>
|
| /external/llvm/test/MC/ARM/ |
| directive-arch-armv7-a.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv7-a
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 7-
[all...] |
| directive-arch-armv7-r.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv7-r
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 7-
[all...] |
| directive-arch-armv7a.s | 3 @ This test case will check the default .ARM.attributes value for the
7 @ RUN: | FileCheck %s -check-prefix CHECK-ASM
9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
14 @ CHECK-ASM: .arch armv7-a
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 7-
[all...] |
