| /external/llvm/test/CodeGen/X86/ |
| sse2-mul.ll | 6 ; CHECK-LABEL: test1:
7 ; CHECK: pshufd $49
8 ; CHECK: pmuludq
9 ; CHECK: pshufd $49
10 ; CHECK: pmuludq
11 ; CHECK: shufps $-120
12 ; CHECK: pshufd $-40
13 ; CHECK: ret
|
| trunc-ext-ld-st.ll | 3 ;CHECK-LABEL: load_2_i8:
5 ;CHECK: pmovzxbq
6 ;CHECK: paddq
7 ;CHECK: pshufb
9 ;CHECK: movw
10 ;CHECK: ret
19 ;CHECK-LABEL: load_2_i16:
21 ;CHECK: pmovzxwq
22 ;CHECK: paddq
23 ;CHECK: pshuf
[all...] |
| /external/llvm/test/CodeGen/XCore/ |
| constants.ll | 3 ; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
4 ; CHECK: .LCPI0_0:
5 ; CHECK: .long 12345678
6 ; CHECK-LABEL: f:
7 ; CHECK: ldw r0, cp[.LCPI0_0]
15 ; CHECK-LABEL: g:
16 ; CHECK: mkmsk r0, 1
17 ; CHECK: retsp 0
|
| /external/llvm/test/FileCheck/ |
| next-no-match.txt | 5 ; CHECK: foo
7 ; CHECK-NEXT: baz
|
| /external/llvm/test/MC/ARM/ |
| directive-literals.s | 9 @ CHECK-LABEL: short
10 @ CHECK-NEXT: .short 0
11 @ CHECK-NEXT: .short 57086
17 @ CHECK-LABEL: hword
18 @ CHECK-NEXT: .short 0
19 @ CHECK-NEXT: .short 57086
24 @ CHECK-LABEL: word
25 @ CHECK-NEXT: .long 3
|
| inst-directive-emit.s | 12 @ CHECK: .text
13 @ CHECK: .code 16
14 @ CHECK: .align 2
15 @ CHECK: .globl emit_asm
16 @ CHECK: .type emit_asm,%function
17 @ CHECK: emit_asm:
18 @ CHECK: inst.w 0xF2400000
19 @ CHECK: inst.w 0xF2C00000
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| unpredictable-ADC-arm.txt | 3 # CHECK: potentially undefined
4 # CHECK: 0x1f 0x12 0xb0 0x00
7 # CHECK: potentially undefined
8 # CHECK: 0x13 0xf2 0xb0 0x00
11 # CHECK: potentially undefined
12 # CHECK: 0x13 0x1f 0xb0 0x00
15 # CHECK: potentially undefined
16 # CHECK: 0x13 0x12 0xbf 0x00
|
| unpredictable-ADDREXT3-arm.txt | 3 # CHECK: potentially undefined
4 # CHECK: 0xd1 0xf1 0x5f 0x01
6 # CHECK: potentially undefined
7 # CHECK: 0xf1 0xf1 0x5f 0x01
9 # CHECK: potentially undefined
10 # CHECK: 0xf1 0xf1 0x5f 0x01
12 # CHECK: potentially undefined
13 # CHECK: 0xd1 0xe1 0x4f 0x01
|
| unpredictable-MUL-arm.txt | 3 # CHECK: potentially undefined
4 # CHECK: 0x93 0x12 0x01 0x00
7 # CHECK: potentially undefined
8 # CHECK: 0x92 0x0f 0x01 0x00
11 # CHECK: potentially undefined
12 # CHECK: 0x9f 0x02 0x01 0x00
15 # CHECK: potentially undefined
16 # CHECK: 0x92 0x01 0x0f 0x00
|
| /external/llvm/test/MC/ELF/ |
| org.s | 8 // CHECK: Section {
9 // CHECK: Name: .text
10 // CHECK-NEXT: Type:
11 // CHECK-NEXT: Flags [
12 // CHECK: ]
13 // CHECK-NEXT: Address:
14 // CHECK-NEXT: Offset:
15 // CHECK-NEXT: Size: 20
|
| /external/llvm/test/MC/X86/ |
| x86_64-rtm-encoding.s | 3 // CHECK: xbegin .L0
4 // CHECK: encoding: [0xc7,0xf8,A,A,A,A]
7 // CHECK: xend
8 // CHECK: encoding: [0x0f,0x01,0xd5]
11 // CHECK: xtest
12 // CHECK: encoding: [0x0f,0x01,0xd6]
15 // CHECK: xabort
16 // CHECK: encoding: [0xc6,0xf8,0x0d]
|
| /external/llvm/test/Object/ |
| yaml2obj-elf-file-headers-with-e_flags.yaml | 10 # CHECK: Format: ELF32-mips
11 # CHECK: Arch: mipsel
12 # CHECK: Machine: EM_MIPS
13 # CHECK: Flags [ (0x70001001)
14 # CHECK-NEXT: EF_MIPS_ABI_O32 (0x1000)
15 # CHECK-NEXT: EF_MIPS_ARCH_32R2 (0x70000000)
16 # CHECK-NEXT: EF_MIPS_NOREORDER (0x1)
17 # CHECK-NEXT: ]
|
| /external/llvm/test/TableGen/ |
| listconcat.td | 3 // CHECK: class Y<list<string> Y:S = ?> {
4 // CHECK: list<string> T1 = !listconcat(Y:S, ["foo"]);
5 // CHECK: list<string> T2 = !listconcat(Y:S, !listconcat(["foo"], !listconcat(Y:S, ["bar", "baz"])));
6 // CHECK: }
8 // CHECK: def Z {
9 // CHECK: list<string> T1 = ["fu", "foo"];
10 // CHECK: list<string> T2 = ["fu", "foo", "fu", "bar", "baz"];
11 // CHECK: }
|
| /external/valgrind/main/memcheck/tests/ |
| leak_cpp_interior.vgtest | 2 vgopts: --leak-check=summary --leak-check-heuristics=multipleinheritance,stdstring,newarray
|
| /frameworks/compile/libbcc/tests/debuginfo/host-tests/ |
| jit.cpp | 7 // CHECK: #0
8 // CHECK: three () at
9 // CHECK: #1
10 // CHECK: in two
11 // CHECK: #2
12 // CHECK: in one
13 // CHECK: #3
14 // CHECK: in main
|
| /external/clang/test/CodeGen/ |
| rdrand-builtins.c | 10 // CHECK: @rdrand16
11 // CHECK: call { i16, i32 } @llvm.x86.rdrand.16
12 // CHECK: store i16
17 // CHECK: @rdrand32
18 // CHECK: call { i32, i32 } @llvm.x86.rdrand.32
19 // CHECK: store i32
24 // CHECK: @rdrand64
25 // CHECK: call { i64, i32 } @llvm.x86.rdrand.64
26 // CHECK: store i64
31 // CHECK: @rdseed1
[all...] |
| /external/clang/test/CodeGenCXX/ |
| mangle-local-class-vtables.cpp | 3 // CHECK: @_ZTVZN1J1KEvE1C = {{.*}} @_ZTIZN1J1KEvE1C {{.*}} @_ZZN1J1KEvENK1C1FEv
4 // CHECK: @_ZTIZN1J1KEvE1C = {{.*}} @_ZTSZN1J1KEvE1C
5 // CHECK: @_ZTVZ1GvE1C_1 = {{.*}} @_ZTIZ1GvE1C_1 {{.*}} @_ZZ1GvENK1C1FE_1v
6 // CHECK: @_ZTIZ1GvE1C_1 = {{.*}} @_ZTSZ1GvE1C_1
7 // CHECK: @_ZTVZ1GvE1C_0 = {{.*}} @_ZTIZ1GvE1C_0 {{.*}} @_ZZ1GvENK1C1FE_0v
8 // CHECK: @_ZTIZ1GvE1C_0 = {{.*}} @_ZTSZ1GvE1C_0
9 // CHECK: @_ZTVZ1GvE1C = {{.*}} @_ZTIZ1GvE1C {{.*}} @_ZZ1GvENK1C1FEv
10 // CHECK: @_ZTIZ1GvE1C = {{.*}} @_ZTSZ1GvE1C
12 // CHECK: define {{.*}} @_ZZN1J1KEvEN1CC2Ev(
13 // CHECK: define {{.*}} @_ZZN1J1KEvENK1C1FEv
[all...] |
| /external/clang/test/Layout/ |
| ms-x86-misalignedarray.cpp | 4 // RUN: | FileCheck %s -check-prefix CHECK-X64
10 // CHECK: *** Dumping AST Record Layout
11 // CHECK: *** Dumping AST Record Layout
12 // CHECK: *** Dumping AST Record Layout
13 // CHECK-NEXT: 0 | struct T3
14 // CHECK-NEXT: 0 | struct T2 [1] a
15 // CHECK-NEXT: 5 | char c
16 // CHECK-NEXT: | [sizeof=8, align=4
17 // CHECK-NEXT: | nvsize=8, nvalign=4
[all...] |
| /external/clang/test/Preprocessor/ |
| macho-embedded-predefines.c | 1 // RUN: %clang_cc1 -E -dM -triple thumbv7m-apple-unknown-macho -target-cpu cortex-m3 %s | FileCheck %s -check-prefix CHECK-7M
3 // CHECK-7M: #define __APPLE_CC__
4 // CHECK-7M: #define __APPLE__
5 // CHECK-7M: #define __ARM_ARCH_7M__
6 // CHECK-7M-NOT: #define __MACH__
8 // RUN: %clang_cc1 -E -dM -triple thumbv7em-apple-unknown-macho -target-cpu cortex-m4 %s | FileCheck %s -check-prefix CHECK-7EM
10 // CHECK-7EM: #define __APPLE_CC__
11 // CHECK-7EM: #define __APPLE_
[all...] |
| /external/clang/test/Sema/ |
| ms_bitfield_layout.c | 16 // CHECK: Type: struct A
17 // CHECK: Size:128
18 // CHECK: Alignment:32
19 // CHECK: FieldOffsets: [0, 32, 64, 64, 96, 99, 112]>
28 // CHECK: Type: struct B
29 // CHECK: Size:48
30 // CHECK: Alignment:16
31 // CHECK: FieldOffsets: [0, 8, 16, 32]>
40 // CHECK: Type: struct C
41 // CHECK: Size:64
[all...] |
| /external/llvm/test/Assembler/ |
| aggregate-constant-values.ll | 3 ; CHECK: @foo
4 ; CHECK: store { i32, i32 } { i32 7, i32 9 }, { i32, i32 }* %x
5 ; CHECK: ret
11 ; CHECK: @foo_empty
12 ; CHECK: store {} zeroinitializer, {}* %x
13 ; CHECK: ret
19 ; CHECK: @bar
20 ; CHECK: store [2 x i32] [i32 7, i32 9], [2 x i32]* %x
21 ; CHECK: ret
27 ; CHECK: @bar_empt
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vshuffle.ll | 5 ; CHECK: lCPI0_0:
6 ; CHECK: .byte 2 ; 0x2
7 ; CHECK: .byte 255 ; 0xff
8 ; CHECK: .byte 6 ; 0x6
9 ; CHECK: .byte 255 ; 0xff
12 ; CHECK: .byte 2 ; 0x2
13 ; CHECK: .byte 4 ; 0x4
14 ; CHECK: .byte 6 ; 0x6
15 ; CHECK: .byte 0 ; 0x0
16 ; CHECK: test
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| float-asmprint.ll | 3 ; Check that all current floating-point types are correctly emitted to assembly
13 ; CHECK: var128:
14 ; CHECK-NEXT: .quad -9223372036854775808 # fp128 -0
15 ; CHECK-NEXT: .quad 0
16 ; CHECK-NEXT: .size
18 ; CHECK: varppc128:
19 ; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0
20 ; CHECK-NEXT: .quad 0
21 ; CHECK-NEXT: .size
23 ; CHECK: var64
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| fp-conv-10.ll | 12 ; CHECK-LABEL: f1:
13 ; CHECK: cebr
14 ; CHECK: sebr
15 ; CHECK: cfebr
16 ; CHECK: xilf
17 ; CHECK: br %r14
24 ; CHECK-LABEL: f2:
25 ; CHECK: cdbr
26 ; CHECK: sdbr
27 ; CHECK: cfdb
[all...] |
| fp-conv-12.ll | 11 ; CHECK-LABEL: f1:
12 ; CHECK: cebr
13 ; CHECK: sebr
14 ; CHECK: cgebr
15 ; CHECK: xihf
16 ; CHECK: br %r14
23 ; CHECK-LABEL: f2:
24 ; CHECK: cdbr
25 ; CHECK: sdbr
26 ; CHECK: cgdb
[all...] |
