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  /external/llvm/test/CodeGen/ARM/
fast-isel-br-const.ll 47 declare void @foo1()
49 declare void @foo2()
fp.ll 75 declare void @f4(double)
77 declare double @f5()
ldm.ll 44 declare i32 @f1(i32, i32)
46 declare i32 @f2(i32, i32, i32)
optimize-dmbs-v7.ll 73 declare void @llvm.arm.dmb(i32)
74 declare void @llvm.arm.dsb(i32)
pr3502.ll 22 declare i32 @SetCurrEntry(i32, i32)
24 declare void @ClearStuff(i32)
vshiftins.ll 147 declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
148 declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
149 declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
150 declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone
152 declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
153 declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
154 declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
155 declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
vshl.ll 344 declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
345 declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
346 declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
347 declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
349 declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
350 declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
351 declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
352 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
354 declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
355 declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnon
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  /external/llvm/test/CodeGen/Generic/
badarg6.ll 7 declare i32 @printf(i8*, ...)
9 declare double @opaque(double)
  /external/llvm/test/CodeGen/Hexagon/
always-ext.ll 19 declare void @_Assert()
45 declare void @llvm.trap() noreturn nounwind
  /external/llvm/test/CodeGen/Mips/
2011-05-26-BranchKillsVreg.ll 40 declare i8* @memmove(i8*, i8*, i32)
42 declare void @free(i8*)
eh-dwarf-cfa.ll 7 declare i8* @llvm.eh.dwarf.cfa(i32) nounwind
8 declare i8* @llvm.frameaddress(i32) nounwind readnone
f16abs.ll 28 declare double @fabs(double) #1
30 declare float @fabsf(float) #1
fp-spill-reload.ll 36 declare void @foo2(i32, i32, i32, i32, i32, i32, i32, i32)
38 declare void @foo1(...)
largeimmprinting.ll 36 declare void @f2(%struct.S1* byval)
38 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
mbrsize4a.ll 29 declare i32 @foo(...) #1
31 declare i32 @printf(i8*, ...) #1
nacl-branch-delay.ll 8 declare void @f1(i32)
9 declare void @f2()
simplebr.ll 30 declare void @goo(...) #1
32 declare void @hoo(...) #1
spill-copy-acreg.ll 19 declare i64 @llvm.mips.maddu(i64, i32, i32)
21 declare void @foo1()
  /external/llvm/test/CodeGen/Mips/msa/
2rf_tq.ll 20 declare <8 x i16> @llvm.mips.ftq.h(<4 x float>, <4 x float>) nounwind
42 declare <4 x i32> @llvm.mips.ftq.w(<2 x double>, <2 x double>) nounwind
3r-p.ll 20 declare <16 x i8> @llvm.mips.pckev.b(<16 x i8>, <16 x i8>) nounwind
42 declare <8 x i16> @llvm.mips.pckev.h(<8 x i16>, <8 x i16>) nounwind
64 declare <4 x i32> @llvm.mips.pckev.w(<4 x i32>, <4 x i32>) nounwind
86 declare <2 x i64> @llvm.mips.pckev.d(<2 x i64>, <2 x i64>) nounwind
108 declare <16 x i8> @llvm.mips.pckod.b(<16 x i8>, <16 x i8>) nounwind
130 declare <8 x i16> @llvm.mips.pckod.h(<8 x i16>, <8 x i16>) nounwind
152 declare <4 x i32> @llvm.mips.pckod.w(<4 x i32>, <4 x i32>) nounwind
174 declare <2 x i64> @llvm.mips.pckod.d(<2 x i64>, <2 x i64>) nounwind
3rf_exdo.ll 20 declare <8 x half> @llvm.mips.fexdo.h(<4 x float>, <4 x float>) nounwind
42 declare <4 x float> @llvm.mips.fexdo.w(<2 x double>, <2 x double>) nounwind
3rf_float_int.ll 20 declare <4 x float> @llvm.mips.fexp2.w(<4 x float>, <4 x i32>) nounwind
42 declare <2 x double> @llvm.mips.fexp2.d(<2 x double>, <2 x i64>) nounwind
elm_shift_slide.ll 20 declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind
41 declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind
62 declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind
83 declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32) nounwind
102 declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32) nounwind
121 declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32) nounwind
140 declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32) nounwind
159 declare <2 x i64> @llvm.mips.splati.d(<2 x i64>, i32) nounwind
special.ll 18 declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
41 declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
vecs10.ll 20 declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind
41 declare i32 @llvm.mips.bz.v(<16 x i8>) nounwind

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<<71727374757677787980>>