| /external/scrypt/ |
| import_scrypt.sh | 38 declare -r message=$1
45 declare -r message=$1
83 declare -r command=$1
86 declare -r tar=$1
90 declare -r patch=$1
96 declare -r patch=$1
98 declare -r tar=$1
160 declare -r pattern=$1
183 declare -r tmpfile=$(mktemp)
186 declare -r cflags=$(filter_by_egrep "^-D" $(grep -e "^CFLAG=" $tmpfile)
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| avx512-intrinsics.ll | 3 declare i32 @llvm.x86.avx512.kortestz.w(i16, i16) nounwind readnone
12 declare i32 @llvm.x86.avx512.kortestc.w(i16, i16) nounwind readnone
21 declare i16 @llvm.x86.avx512.kand.w(i16, i16) nounwind readnone
31 declare i16 @llvm.x86.avx512.knot.w(i16) nounwind readnone
39 declare i16 @llvm.x86.avx512.kunpck.bw(i16, i16) nounwind readnone
54 declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone
61 declare <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double>, <8 x double>, i8) nounwind readnone
68 declare <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
75 declare <8 x double> @llvm.x86.avx512.rcp28.pd(<8 x double>, <8 x double>, i8, i32) nounwind readnone
77 declare <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double>, i32, <8 x double>, i8, i32
[all...] |
| avx-intrinsics-x86.ll | 8 declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone
16 declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind readnone
24 declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone
32 declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind readnone
40 declare <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64>) nounwind readnone
48 declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) nounwind readnone
56 declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
64 declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
72 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
82 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnon
[all...] |
| fma3-intrinsics.ll | 10 declare <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
17 declare <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
24 declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
31 declare <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
38 declare <4 x float> @llvm.x86.fma.vfnmadd.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
45 declare <8 x float> @llvm.x86.fma.vfnmadd.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
53 declare <4 x float> @llvm.x86.fma.vfmsub.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
60 declare <4 x float> @llvm.x86.fma.vfmsub.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
67 declare <4 x float> @llvm.x86.fma.vfnmsub.ss(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
74 declare <4 x float> @llvm.x86.fma.vfnmsub.ps(<4 x float>, <4 x float>, <4 x float>) nounwind readnon
[all...] |
| rounding-ops.ll | 15 declare float @floorf(float) nounwind readnone
28 declare double @floor(double) nounwind readnone
41 declare float @nearbyintf(float) nounwind readnone
54 declare double @nearbyint(double) nounwind readnone
67 declare float @ceilf(float) nounwind readnone
80 declare double @ceil(double) nounwind readnone
93 declare float @rintf(float) nounwind readnone
106 declare double @rint(double) nounwind readnone
119 declare float @truncf(float) nounwind readnone
132 declare double @trunc(double) nounwind readnon
[all...] |
| sse41-intrinsics-x86.ll | 8 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i32) nounwind readnone
16 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i32) nounwind readnone
24 declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
32 declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
40 declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i32) nounwind readnone
48 declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i32) nounwind readnone
56 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
65 declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i32) nounwind readnone
73 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
81 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnon
[all...] |
| /external/bison/tests/ |
| cxx-type.at | 109 { $$ = new_nterm ("<declare>(%s,%s)", ]$[1, ]$[2, YY_NULL); }
111 { $$ = new_nterm ("<init-declare>(%s,%s,%s)", ]$[1,
328 <declare>(T,x)
329 <init-declare>(T,x,y)
332 <declare>(T,x)
333 <init-declare>(T,y,+(z,q))
340 5.0-5.3: <declare>(T,x)
341 7.0-7.7: <init-declare>(T,x,y)
344 13.0-13.5: <declare>(T,x)
345 15.0-15.13: <init-declare>(T,y,+(z,q)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/glsl/builtins/ir/ |
| transpose.ir | 4 (declare (in) mat2 m))
5 ((declare () mat2 t)
14 (declare (in) mat2x3 m))
15 ((declare () mat3x2 t)
26 (declare (in) mat2x4 m))
27 ((declare () mat4x2 t)
40 (declare (in) mat3x2 m))
41 ((declare () mat2x3 t)
52 (declare (in) mat3 m))
53 ((declare () mat3 t
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| vqshrn.ll | 75 declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
76 declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
77 declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
79 declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
80 declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
81 declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
83 declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
84 declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
85 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
159 declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnon
[all...] |
| 2009-08-31-LSDA-Name.ll | 73 declare i8* @_Znwm(i32)
94 declare void @_ZdlPv(i8*) nounwind
96 declare void @_Z3barv()
98 declare i32 @llvm.eh.typeid.for(i8*) nounwind
100 declare i32 @__gxx_personality_sj0(...)
102 declare void @_Unwind_SjLj_Resume(i8*)
|
| /external/llvm/test/CodeGen/Generic/ |
| overflow.ll | 15 declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8) nounwind readnone
26 declare { i16, i1 } @llvm.sadd.with.overflow.i16(i16, i16) nounwind readnone
37 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
51 declare { i8, i1 } @llvm.uadd.with.overflow.i8(i8, i8) nounwind readnone
62 declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) nounwind readnone
73 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
88 declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8) nounwind readnone
99 declare { i16, i1 } @llvm.ssub.with.overflow.i16(i16, i16) nounwind readnone
110 declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
124 declare { i8, i1 } @llvm.usub.with.overflow.i8(i8, i8) nounwind readnon
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| ctrloop-reg.ll | 29 declare i32 @zadd(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
31 declare i32 @zdup(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
33 declare i32 @zexch(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
35 declare i32 @zifelse(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
37 declare i32 @zle(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
39 declare i32 @zpop(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
41 declare i32 @zsub(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211*)
43 declare void @interp_init(i32) nounwind
45 declare void @interp_fix_op(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211* nocapture) nounwind
71 declare i32 @interp_exit(%struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211* nocapture) nou (…)
[all...] |
| /external/mesa3d/src/glsl/builtins/ir/ |
| transpose.ir | 4 (declare (in) mat2 m))
5 ((declare () mat2 t)
14 (declare (in) mat2x3 m))
15 ((declare () mat3x2 t)
26 (declare (in) mat2x4 m))
27 ((declare () mat4x2 t)
40 (declare (in) mat3x2 m))
41 ((declare () mat2x3 t)
52 (declare (in) mat3 m))
53 ((declare () mat3 t
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-cvt.ll | 38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone
41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone
78 declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone
79 declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone
80 declare i32 @llvm.aarch64.neon.fcvtau.i32.f64(double) nounwind readnone
81 declare i64 @llvm.aarch64.neon.fcvtau.i64.f64(double) nounwind readnone
118 declare i32 @llvm.aarch64.neon.fcvtms.i32.f32(float) nounwind readnone
119 declare i64 @llvm.aarch64.neon.fcvtms.i64.f32(float) nounwind readnon
[all...] |
| arm64-neon-across.ll | 3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>
[all...] |
| arm64-smaxv.ll | 68 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
69 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
70 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
71 declare i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32>)
72 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
73 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
|
| arm64-sminv.ll | 68 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
69 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
70 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
71 declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)
72 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
73 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
|
| arm64-vcnt.ll | 51 declare <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8>) nounwind readnone
52 declare <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8>) nounwind readnone
53 declare <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16>) nounwind readnone
54 declare <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16>) nounwind readnone
55 declare <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32>) nounwind readnone
56 declare <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32>) nounwind readnone
|
| arm64-vcvt_n.ll | 44 declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
45 declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
46 declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
47 declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
48 declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
49 declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
|
| arm64-vhadd.ll | 111 declare <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
112 declare <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
113 declare <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
115 declare <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
116 declare <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
117 declare <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
119 declare <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
120 declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
123 declare <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnon
[all...] |
| arm64-vsqrt.ll | 30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
62 declare <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
64 declare <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double>, <2 x double>) nounwind readnone
106 declare <2 x float> @llvm.aarch64.neon.frecpe.v2f32(<2 x float>) nounwind readnone
107 declare <4 x float> @llvm.aarch64.neon.frecpe.v4f32(<4 x float>) nounwind readnone
108 declare <2 x double> @llvm.aarch64.neon.frecpe.v2f64(<2 x double>) nounwind readnone
109 declare float @llvm.aarch64.neon.frecpe.f32(float) nounwind readnon
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| malloc-free-delete.ll | 14 declare noalias i8* @calloc(i32, i32) nounwind
15 declare noalias i8* @malloc(i32)
16 declare void @free(i8*)
27 declare void @llvm.lifetime.start(i64, i8*)
28 declare void @llvm.lifetime.end(i64, i8*)
29 declare i64 @llvm.objectsize.i64(i8*, i1)
30 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
31 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
32 declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1) nounwind
124 declare i8* @_ZnwmRKSt9nothrow_t(i64, i8*) nobuilti
[all...] |
| /external/llvm/test/Transforms/InstSimplify/ |
| call.ll | 3 declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
21 declare i256 @llvm.cttz.i256(i256 %src, i1 %is_zero_undef)
30 declare i256 @llvm.ctpop.i256(i256 %src)
40 declare float @fabs(float %x)
55 declare float @llvm.fabs.f32(float) nounwind readnone
56 declare float @llvm.floor.f32(float) nounwind readnone
57 declare float @llvm.ceil.f32(float) nounwind readnone
58 declare float @llvm.trunc.f32(float) nounwind readnone
59 declare float @llvm.rint.f32(float) nounwind readnone
60 declare float @llvm.nearbyint.f32(float) nounwind readnon
[all...] |
| /external/llvm/test/Transforms/ObjCARC/ |
| rv.ll | 5 declare i8* @objc_retain(i8*)
6 declare i8* @objc_retainAutoreleasedReturnValue(i8*)
7 declare void @objc_release(i8*)
8 declare i8* @objc_autorelease(i8*)
9 declare i8* @objc_autoreleaseReturnValue(i8*)
10 declare i8* @objc_retainAutoreleaseReturnValue(i8*)
11 declare void @objc_autoreleasePoolPop(i8*)
12 declare void @objc_autoreleasePoolPush()
13 declare i8* @objc_retainBlock(i8*)
15 declare i8* @objc_retainedObject(i8*
[all...] |
| /external/clang/test/CodeGenCXX/ |
| visibility-ms-compat.cpp | 26 // CHECK: declare void @_ZN5test01A3barEv()
42 // CHECK: declare hidden void @_ZN5test11A3barEv()
58 // CHECK: declare void @_ZN5test21A3barEv()
75 // CHECK: declare void @_ZN5test31BINS_1AEE3barEv()
91 // CHECK: declare void @_ZN5test41BINS_1AEE3barEv()
107 // CHECK: declare hidden void @_ZN5test51BINS_1AEE3barEv()
|
