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  /external/llvm/test/CodeGen/ARM/
arm-modifier.ll 1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 -no-integrated-as %s -o - | FileCheck %s
big-endian-neon-extend.ll 1 ; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
fpcmp-opt.ll 1 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
fpconv.ll 1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
inlineasm3.ll 1 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as %s -o - \
mvn.ll 1 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
neon_minmax.ll 1 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
unaligned_load_store.ll 1 ; RUN: llc -mtriple=arm-eabi -pre-RA-sched=source %s -o - \
interrupt-attr.ll 1 ; RUN: llc -mtriple=arm-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A %s
2 ; RUN: llc -mtriple=thumb-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s
vld1.ll 1 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
3 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \
vcgt.ll 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s
vld3.ll 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o -| FileCheck %s
2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s
  /external/llvm/test/CodeGen/Thumb2/
thumb2-bic.ll 1 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
thumb2-cmn.ll 1 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
  /external/llvm/test/MC/ARM/
directive-arch_extension-simd.s 1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
3 @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
5 @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
7 @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
eh-directive-personalityindex-diagnostics.s 1 @ RUN: not llvm-mc -triple armv7-linux-eabi -filetype asm -o /dev/null %s 2>&1 \
eh-directive-unwind_raw.s 1 @ RUN: llvm-mc -triple armv7-linux-eabi -filetype obj -o - %s | llvm-readobj -u \
vfp-aliases-diagnostics.s 1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 \
  /frameworks/rs/cpu_ref/
rsCpuRuntimeMathFuncs.cpp 105 // pick the simplest implementation based on the ARM EABI doc.
  /frameworks/compile/mclinker/tools/mcld/lib/
TripleOptions.cpp 46 /// name. For example, if the program name is `arm-linux-eabi-ld.mcld', we can
47 /// get the triple is arm-linux-eabi by the program name.
  /prebuilts/qemu-kernel/arm/
rebuild.sh 113 TOOLCHAIN_NAME=arm-eabi-4.4.0
114 TOOLCHAIN_PREFIX=arm-eabi
  /external/llvm/unittests/ADT/
TripleTest.cpp 126 T = Triple("arm-none-none-eabi");
130 EXPECT_EQ(Triple::EABI, T.getEnvironment());
249 EXPECT_EQ("arm-none--eabi", Triple::normalize("arm-none-eabi")); // arm-none-eabi
  /external/clang/docs/
CrossCompilation.rst 85 * ``abi`` = ``eabi``, ``gnu``, ``android``, ``macho``, ``elf``, etc.
122 For example, if your target is ``arm-none-eabi``, the default CPU will
124 whereas if your triple is ``armv7a-none-eabi``, it'll be Cortex-A8 with
  /external/llvm/lib/Target/ARM/
ARMCallingConv.td 110 // ARM AAPCS (EABI) Calling Convention, common parts
138 // ARM AAPCS (EABI) Calling Convention
165 // ARM AAPCS-VFP (EABI) Calling Convention
  /external/strace/
configure.ac 155 [enable OABI support on ARM EABI])],
163 [Define to 1 if you want OABI support on ARM EABI.])

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