| /external/valgrind/main/none/tests/mips64/ |
| move_instructions.stdout.exp-BE | 0 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
3 mtc1, mov.s, mfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
5 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
7 mtc1, mov.s, mfc1 :: mem: 0x7e876382d2ab13 out: 0xffffffff82d2ab13
9 mtc1, mov.s, mfc1 :: mem: 0x9823b6e out: 0x9823b6e
11 mtc1, mov.s, mfc1 :: mem: 0x976d6e9ac31510f3 out: 0xffffffffc31510f3
13 mtc1, mov.s, mfc1 :: mem: 0xd4326d9 out: 0xd4326d9
15 mtc1, mov.s, mfc1 :: mem: 0xb7746d775ad6a5fb out: 0x5ad6a5fb
17 mtc1, mov.s, mfc1 :: mem: 0x130476dc out: 0x130476dc
19 mtc1, mov.s, mfc1 :: mem: 0x42b0c0a28677b502 out: 0xffffffff8677b50
[all...] |
| move_instructions.stdout.exp-LE | 0 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
3 mtc1, mov.s, mfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
5 mtc1, mov.s, mfc1 :: mem: 0x0 out: 0x0
7 mtc1, mov.s, mfc1 :: mem: 0x7e876382d2ab13 out: 0xffffffff82d2ab13
9 mtc1, mov.s, mfc1 :: mem: 0x9823b6e out: 0x9823b6e
11 mtc1, mov.s, mfc1 :: mem: 0x976d6e9ac31510f3 out: 0xffffffffc31510f3
13 mtc1, mov.s, mfc1 :: mem: 0xd4326d9 out: 0xd4326d9
15 mtc1, mov.s, mfc1 :: mem: 0xb7746d775ad6a5fb out: 0x5ad6a5fb
17 mtc1, mov.s, mfc1 :: mem: 0x130476dc out: 0x130476dc
19 mtc1, mov.s, mfc1 :: mem: 0x42b0c0a28677b502 out: 0xffffffff8677b50
[all...] |
| macro_fpu.h | 116 "mtc1 %2, $f0" "\n\t" \
127 "mtc1 %2, $f0" "\n\t" \
223 "mtc1 $zero, $f0" "\n\t" \
271 "mtc1 $zero, $f0" "\n\t" \
|
| /external/llvm/test/CodeGen/Mips/ |
| 2008-08-04-Bitconvert.ll | 5 ; CHECK: mtc1
|
| 2013-11-18-fp64-const0.ll | 13 ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[02468]}}
14 ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[13579]}}
16 ; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}}
17 ; CHECK-FP64-NOT: mtc1 $zero,
|
| constantfp0.ll | 5 ; CHECK: mtc1 $zero, $f[[R0:[0-9]+]]
|
| buildpairextractelementf64.ll | 9 ; FP32: mtc1
10 ; FP32: mtc1
11 ; FP64-DAG: mtc1
|
| fmadd1.ll | 25 ; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
28 ; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
31 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
33 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
36 ; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
39 ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
44 ; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
48 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
53 ; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
66 ; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]
[all...] |
| int-to-float-conversion.ll | 9 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
19 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
22 ; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
|
| select.ll | 135 ; 32-DAG: mtc1 $5, $[[F0:f[0-9]+]]
136 ; 32-DAG: mtc1 $6, $[[F1:f0]]
139 ; 32R2-DAG: mtc1 $5, $[[F0:f[0-9]+]]
140 ; 32R2-DAG: mtc1 $6, $[[F1:f0]]
143 ; 32R6-DAG: mtc1 $5, $[[F0:f[0-9]+]]
144 ; 32R6-DAG: mtc1 $6, $[[F1:f[0-9]+]]
146 ; 32R6: mtc1 $[[T0]], $[[CC:f0]]
156 ; 64R6: mtc1 $[[T0]], $[[CC:f0]]
168 ; 32-DAG: mtc1 $6, $[[F0:f[1-3]*[02468]+]]
169 ; 32-DAG: mtc1 $7, $[[F0H:f[1-3]*[13579]+]
[all...] |
| fcopysign.ll | 16 ; 32: mtc1 $[[OR]], $f1
49 ; 32: mtc1 $[[OR]], $f0
53 ; 32R2: mtc1 $[[INS]], $f0
|
| hf16call32.ll | [all...] |
| mno-ldc1-sdc1.ll | 57 ; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0
58 ; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1
62 ; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0
67 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
74 ; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0
75 ; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1
81 ; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0
88 ; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0
93 ; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0
94 ; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f
[all...] |
| analyzebranch.ll | 16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
|
| fcopysign-f32-f64.ll | 19 ; 64: mtc1 $[[OR]], $f0
23 ; 64R2: mtc1 $[[INS]], $f0
|
| selectcc.ll | 23 ; SOURCE-SCHED: mtc1
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 62 // mtc1 rt, fs
145 "mtc1 $t0, $f0\n\t" \
146 "mtc1 $t1, $f2\n\t" \
167 "mtc1 $t0, $f0\n\t" \
168 "mtc1 $t1, $f2\n\t" \
192 "mtc1 $t0, $f0\n\t" \
193 "mtc1 %3, $f2\n\t" \
218 "mtc1 $t0, $f0\n\t" \
219 "mtc1 $t1, $f2\n\t" \
246 "mtc1 $0, $" #FD "\n\t"
[all...] |
| MoveIns.stdout.exp | 29 MTC1
30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff
[all...] |
| MoveIns.stdout.exp-BE | 29 MTC1
30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff
[all...] |
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| simplestorefp1.ll | 15 ; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
31 ; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
|
| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/ |
| SOURCES | 9 toolchain/binutils.git fff40e635995d00e3455f861a97d8cbf3ebb6b4e Merge "Add missing mtc1, mthc1, mfhc1 instructions to Ingenic's MXU patch."
|
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/ |
| SOURCES | 9 toolchain/binutils.git fff40e635995d00e3455f861a97d8cbf3ebb6b4e Merge "Add missing mtc1, mthc1, mfhc1 instructions to Ingenic's MXU patch."
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| ret.ll | 151 ; NO-MTHC1-DAG: mtc1 $zero, $f0
153 ; MTHC1-DAG: mtc1 $zero, $f0
180 ; NO-MTHC1-DAG: mtc1 $zero, $f0
181 ; NO-MTHC1-DAG: mtc1 $zero, $f1
183 ; MTHC1-DAG: mtc1 $zero, $f0
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-hard-float-varargs.ll | 48 ; O32BE-DAG: mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
49 ; O32BE-DAG: mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
50 ; O32LE-DAG: mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
51 ; O32LE-DAG: mtc1 $5, [[FTMP2:\$f[0-9]*[13579]+]]
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 101 /// MTC1 F4, A5
105 /// instruction between MTC1 and CVT_D32_W.
|
