| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-hard-float.ll | 178 ; O32LE-DAG: mtc1 $6, [[F1:\$f[0-9]*[02468]+]]
179 ; O32LE-DAG: mtc1 $7, [[F2:\$f[0-9]*[13579]+]]
180 ; O32BE-DAG: mtc1 $6, [[F2:\$f[0-9]*[13579]+]]
181 ; O32BE-DAG: mtc1 $7, [[F1:\$f[0-9]*[02468]+]]
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 121 Opc = Mips::MTC1;
301 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
304 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
310 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
547 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
554 // mtc1 Lo, $fp
563 // mtc1 Lo, $fp
564 // mtc1 Hi, $fp + 1
|
| MicroMipsInstrFPU.td | 124 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
|
| MipsInstrFPU.td | 363 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
567 // This pseudo instr gets expanded into 2 mtc1 instrs after register
602 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
603 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
| MipsFastISel.cpp | 328 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
|
| MipsAsmPrinter.cpp | 735 // Because of the current td files for Mips32, the operands for MTC1
739 if (Opcode == Mips::MTC1) {
775 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
[all...] |
| /external/valgrind/main/none/tests/mips64/ |
| move_instructions.c | 56 "mtc1 $t0, $f0" "\n\t" \
66 printf("mtc1, mov.s, mfc1 :: mem: 0x%llx out: 0x%llx\n", \
98 "mtc1 $t0, $f0" "\n\t" \
99 "mtc1 $t1, $f2" "\n\t" \
122 "mtc1 $t0, $f0" "\n\t" \
123 "mtc1 $t1, $f2" "\n\t" \
|
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips.cc | 284 __ mtc1(t0, f14);
360 __ mtc1(t0, f6);
361 __ mtc1(t1, f7);
362 __ mtc1(t2, f4);
363 __ mtc1(t3, f5);
371 __ mtc1(t0, f6);
373 __ mtc1(t2, f4);
434 __ mtc1(t0, f12);
439 __ mtc1(t1, f14);
795 __ mtc1(t0, f8); // f8 has a 32-bits word
[all...] |
| test-assembler-mips64.cc | 296 __ mtc1(a4, f14);
376 __ mtc1(a4, f5);
449 __ mtc1(a4, f12);
454 __ mtc1(a5, f14);
815 __ mtc1(a4, f8); // f8 LS 32-bits.
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_mips_helpers.c | [all...] |
| /external/llvm/test/CodeGen/Mips/msa/ |
| basic_operations_float.ll | 135 ; MIPS32-NOT: mtc1
194 ; MIPS32-NOT: mtc1
215 ; MIPS32-NOT: mtc1
|
| /external/valgrind/main/none/tests/mips32/ |
| round.c | 115 __asm__ volatile("mtc1 %2, $f0" "\n\t" \
124 __asm__ volatile("mtc1 %2, $f0" "\n\t" \
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| _setjmp.S | 57 mtc1 t1, FPR ; \
|
| setjmp.S | 56 mtc1 t1, FPR ; \
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 61 mtc1 $s8,$f9
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 55 # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
118 # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
177 mtc1 $6, $f8
|
| mips-fpu-instructions.s | 151 # CHECK: mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
186 mtc1 $a2,$f7
|
| /art/compiler/utils/mips/ |
| assembler_mips.h | 122 void Mtc1(FRegister ft, Register rs);
|
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | [all...] |
| /external/chromium_org/third_party/webrtc/modules/audio_processing/aec/ |
| aec_core_mips.c | 56 "mtc1 %[tmp1s], %[randTemp] \n\t"
57 "mtc1 %[tmp2s], %[randTemp2] \n\t"
58 "mtc1 %[tmp3s], %[randTemp3] \n\t"
59 "mtc1 %[tmp4s], %[randTemp4] \n\t"
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 69 mtc1 $s8,$f9
|
| /art/compiler/dex/quick/mips/ |
| utility_mips.cc | 36 /* note the operands are swapped for the mtc1 instr */
|
| /external/chromium_org/v8/src/base/ |
| cpu.cc | 125 "mtc1 $t0, $f1\n\t"
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 296 # CHECK: mtc1 $6, $f7
|
| mips32_le.txt | 302 # CHECK: mtc1 $6, $f7
|
