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  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.td 291 def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
326 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
  /external/chromium_org/third_party/WebKit/ManualTests/
select_hr.html 178 <br><select id = "s10" multiple>
  /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/armv7/
armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S 77 #define sr s10
omxSP_FFTFwd_RToCCS_F32_Sfs_s.S 103 #define st2 s10
  /external/clang/test/CodeGenCXX/
microsoft-abi-static-initializers.cpp 55 static S S10;
  /external/llvm/lib/Target/ARM/
ARMCallingConv.h 165 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
  /external/llvm/test/MC/Disassembler/ARM/
arm-tests.txt 239 # CHECK: vldmdb r2!, {s7, s8, s9, s10, s11}
  /external/lldb/source/Utility/
ARM_DWARF_Registers.cpp 51 case dwarf_s10: return "s10";
278 case dwarf_s10: reg_info.name = "s10"; break;
  /external/llvm/test/CodeGen/X86/
misched-balance.ll 265 %s10 = lshr i32 %l1, 16
270 %sa = add i32 %s5, %s10
  /external/vixl/test/
test-assembler-a64.cc     [all...]
  /external/chromium_org/v8/test/cctest/
test-assembler-arm64.cc     [all...]
  /external/chromium_org/third_party/polymer/components/core-icons/
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    [all...]
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  /external/chromium_org/third_party/polymer/components-chromium/core-icons/
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  /external/lldb/source/Plugins/Process/gdb-remote/
GDBRemoteRegisterContext.cpp 708 static uint32_t g_d5_regs[] = { 36, 37, LLDB_INVALID_REGNUM }; // (s10, s11)
721 static uint32_t g_q2_regs[] = { 34, 35, 36, 37, LLDB_INVALID_REGNUM }; // (d4, d5) -> (s8, s9, s10, s11)
    [all...]
  /external/chromium_org/v8/src/arm/
simulator-arm.h 113 s8, s9, s10, s11, s12, s13, s14, s15, enumerator in enum:v8::internal::Simulator::Register
  /external/clang/test/CodeGen/
x86_32-arguments-darwin.c 66 struct s10 { struct
arm64-arguments.c 47 struct s10 { int f0; int : 0; int : 0; }; struct
48 struct s10 f10(void) {}
  /external/lldb/source/Plugins/ABI/MacOSX-arm/
ABIMacOSX_arm.cpp 69 { "s10", NULL, 4, 0, eEncodingIEEE754 , eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, gdb_arm_s10, LLDB_INVALID_REGNUM }, NULL, NULL},
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  /external/openssl/crypto/aes/asm/
aes-mips.pl 31 ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));
372 $REG_S $s10,$FRAMESIZE-4*$SZREG($sp)
419 $REG_L $s10,$FRAMESIZE-4*$SZREG($sp)
709 $REG_S $s10,$FRAMESIZE-4*$SZREG($sp)
756 $REG_L $s10,$FRAMESIZE-4*$SZREG($sp)
    [all...]
  /art/compiler/utils/arm64/
managed_register_arm64_test.cc     [all...]
  /external/llvm/test/MC/Disassembler/AArch64/
neon-instructions.txt 371 # CHECK: sqsub s20, s10, s7
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