| /external/llvm/test/CodeGen/ARM/ |
| 2011-08-25-ldmia_ret.ll | 19 %call = tail call zeroext i1 @getbool() nounwind
23 %cmp = tail call zeroext i1 @getbool() nounwind
27 %cmp13 = tail call zeroext i1 @getbool() nounwind
31 tail call void @foo(i32 %in1) nounwind
47 %call20 = tail call i32 @bar(i32 %in2) nounwind
72 tail call void @foo(i32 %in2) nounwind
73 %call28 = tail call i32 @getint() nounwind
78 tail call void @foo(i32 %in2) nounwind
82 %cmp42 = tail call zeroext i1 @getbool() nounwind
86 %call50 = tail call i32 @getint() nounwin
[all...] |
| gpr-paired-spill.ll | 6 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
7 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
8 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
9 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
10 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
11 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
12 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
|
| inlineasm3.ll | 24 %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
42 tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind
69 %0 = tail call float asm "flds s15, $0", "=x"() nounwind
79 %0 = tail call double asm "flds s15, $0", "=x"() nounwind
89 %0 = tail call float asm "flds s15, $0", "=t"() nounwind
99 %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
121 %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| call.ll | 3 ; FIXME: We should remove the need for -enable-mips-tail-calls
4 ; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
5 ; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
6 ; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
7 ; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
8 ; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
9 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
10 ; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
144 tail call void %addr()
154 %1 = tail call i32 %addr(
[all...] |
| /external/opencv/cvaux/src/ |
| extendededges.cpp | 137 CvSeq* tail = 0; local
184 if( tail )
186 tail->v_next = newseq;
187 newseq->v_prev = tail;
188 tail = newseq;
192 output = tail = newseq;
204 if( tail )
206 tail->v_next = newseq;
207 newseq->v_prev = tail;
208 tail = newseq
[all...] |
| /libcore/luni/src/main/java/java/util/ |
| ArrayDeque.java | 62 * thus avoiding head and tail wrapping around to equal each
71 * arbitrary number equal to tail if the deque is empty.
76 * The index at which the next element would be added to the tail
79 private transient int tail; field in class:ArrayDeque
115 * when head and tail have wrapped around to become equal.
118 // assert head == tail;
130 tail = n;
141 if (head < tail) {
143 } else if (head > tail) {
146 System.arraycopy(elements, 0, a, headPortionLen, tail);
[all...] |
| /external/chromium_org/v8/test/mjsunit/regress/ |
| regress-1708.js | 39 var tail = head; variable
44 tail[1] = new Array(1000);
45 tail = tail[1];
64 tail[1] = new Array(1000);
65 tail = tail[1];
|
| regress-2073.js | 44 this.tail = null;
60 child.tail = null;
63 this.tail.right = child;
64 this.tail = child;
66 this.head = this.tail = child;
75 if (parent.tail == this) parent.tail = this.left;
|
| /external/compiler-rt/lib/builtins/ppc/ |
| fixtfdi.c | 32 /* If the tail is non-zero, we need to patch in the tail bits. */
39 /* At this point we have the mantissa of |tail| */
40 /* We need to negate it if head and tail have different signs. */
45 /* Now we have the mantissa of tail as a signed 2s-complement integer */
49 /* Shift the tail mantissa into the right position, accounting for the
78 /* If the tail is positive, the correct result is something other than INT64_MIN.
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vpopcnt.ll | 9 %cnt = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %x)
18 %cnt = tail call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> %x)
27 %cnt = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %x)
37 %cnt = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x)
46 %cnt = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %x)
55 %cnt = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x)
64 %cnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
|
| tail-call.ll | 11 tail call fastcc void @callee_stack0()
20 tail call fastcc void @callee_stack0()
33 tail call fastcc void @callee_stack8([8 x i32] undef, i64 42)
45 tail call fastcc void @callee_stack8([8 x i32] undef, i64 42)
59 tail call fastcc void @callee_stack16([8 x i32] undef, i64 42, i64 2)
73 tail call fastcc void @callee_stack8([8 x i32] undef, i64 42)
87 tail call fastcc void @callee_stack16([8 x i32] undef, i64 %b, i64 %a)
|
| /external/llvm/test/CodeGen/X86/ |
| tailcall-largecode.ll | 10 %res = tail call fastcc i32 @callee(i32 %arg)
14 ; Check that the register used for an indirect tail call doesn't
35 ; And tail-call to the target.
37 %res = tail call fastcc i32 %target(i32 1, i32 2, i32 3, i32 4, i32 5,
42 ; Check that the register used for a direct tail call doesn't clobber
66 ; And tail-call to the target.
68 %res = tail call fastcc i32 @manyargs_callee(i32 1, i32 2, i32 3, i32 4,
|
| sha.ll | 8 %0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)
17 %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
27 %0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)
36 %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
46 %0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)
55 %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
65 %0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)
74 %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
84 %0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
95 %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c
[all...] |
| mmx-arith.ll | 16 %tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.b( x86_mmx %tmp4a, x86_mmx %tmp7 ) ; <x86_mmx> [#uses=2]
19 %tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.b( x86_mmx %tmp12, x86_mmx %tmp16 ) ; <x86_mmx> [#uses=2]
28 %tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.b( x86_mmx %tmp28a, x86_mmx %tmp31 ) ; <x86_mmx> [#uses=2]
31 %tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.b( x86_mmx %tmp36, x86_mmx %tmp40 ) ; <x86_mmx> [#uses=2]
55 tail call void @llvm.x86.mmx.emms( )
97 tail call void @llvm.x86.mmx.emms( )
111 %tmp12 = tail call x86_mmx @llvm.x86.mmx.padds.w( x86_mmx %tmp4a, x86_mmx %tmp7 ) ; <x86_mmx> [#uses=2]
114 %tmp21 = tail call x86_mmx @llvm.x86.mmx.paddus.w( x86_mmx %tmp12, x86_mmx %tmp16 ) ; <x86_mmx> [#uses=2]
123 %tmp36 = tail call x86_mmx @llvm.x86.mmx.psubs.w( x86_mmx %tmp28a, x86_mmx %tmp31 ) ; <x86_mmx> [#uses=2]
126 %tmp45 = tail call x86_mmx @llvm.x86.mmx.psubus.w( x86_mmx %tmp36, x86_mmx %tmp40 ) ; <x86_mmx> [#uses=2
[all...] |
| /external/llvm/test/Transforms/ObjCARC/ |
| cfg-hazards.ll | 92 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %a) [[NUW:#[0-9]+]]
118 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %a) [[NUW]]
148 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %a) [[NUW]]
159 %outer = tail call i8* @objc_retain(i8* %a) nounwind
160 %inner = tail call i8* @objc_retain(i8* %a) nounwind
182 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %a) [[NUW]]
192 %outer = tail call i8* @objc_retain(i8* %a) nounwind
193 %inner = tail call i8* @objc_retain(i8* %a) nounwind
215 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %a) [[NUW]]
225 %outer = tail call i8* @objc_retain(i8* %a) nounwin
[all...] |
| /external/chromium_org/third_party/mesa/src/src/glsl/ |
| list.h | 28 * Each doubly-linked list has a sentinel head and tail node. These nodes
30 * pointer being \c NULL. The tail sentinel can be identified by its
34 * tail sentinel or the tail sentinel's \c prev poiner points to the head
45 * - A \c tail pointer that represents the \c prev pointer of the head
46 * sentinel node and the \c next pointer of the tail sentinel node. This
49 * tail sentinel node.
183 * Is this the sentinel at the tail of the list?
284 struct exec_node *tail; member in struct:exec_list
314 head = (exec_node *) & tail;
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| tailcall.ll | 1 ; RUN: llc -march=mipsel -relocation-model=pic -enable-mips-tail-calls < %s | \
4 ; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=STATIC32
5 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -enable-mips-tail-calls \
8 ; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=PIC16
28 %call = tail call i32 @callee1(i32 1, i32 1, i32 1, i32 %a0) nounwind
41 %call = tail call i32 @callee2(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind
54 %call = tail call i32 @callee3(i32 1, i32 1, i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind
67 %call = tail call i32 @callee4(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
98 %call = tail call fastcc i32 @callee5(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9)
120 %call = tail call fastcc i32 @caller8_1(
[all...] |
| o32_cc.ll | 12 tail call void @f0(double 5.000000e+00, double 6.000000e+00) nounwind
24 tail call void @f1(float 8.000000e+00, float 9.000000e+00) nounwind
36 tail call void @f2(float 8.000000e+00, double 6.000000e+00) nounwind
48 tail call void @f3(double 5.000000e+00, float 9.000000e+00) nounwind
62 tail call void @f4(i32 12, i32 13, i32 14, i32 15) nounwind
76 tail call void @f5(double 1.500000e+01, i32 23, double 1.700000e+01) nounwind
89 tail call void @f6(double 2.500000e+01, i32 33, i32 24) nounwind
102 tail call void @f7(float 1.800000e+01, i32 43, i32 34) nounwind
117 tail call void @f8(i32 22, i32 53, i32 44, double 4.000000e+00) nounwind
131 tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwin
[all...] |
| /external/mesa3d/src/glsl/ |
| list.h | 28 * Each doubly-linked list has a sentinel head and tail node. These nodes
30 * pointer being \c NULL. The tail sentinel can be identified by its
34 * tail sentinel or the tail sentinel's \c prev poiner points to the head
45 * - A \c tail pointer that represents the \c prev pointer of the head
46 * sentinel node and the \c next pointer of the tail sentinel node. This
49 * tail sentinel node.
183 * Is this the sentinel at the tail of the list?
284 struct exec_node *tail; member in struct:exec_list
314 head = (exec_node *) & tail;
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| vsx-fma-m.ll | 11 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
13 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
29 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
31 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
34 %2 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
53 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
55 %1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
56 %2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
59 %3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
88 %0 = tail call double @llvm.fma.f64(double %b, double %c, double %a
[all...] |
| /external/llvm/test/CodeGen/Generic/ |
| overflow.ll | 8 %sadd = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
19 %sadd = tail call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 %a, i16 %b)
30 %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
44 %uadd = tail call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
55 %uadd = tail call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %a, i16 %b)
66 %uadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
81 %ssub = tail call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %a, i8 %b)
92 %ssub = tail call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 %a, i16 %b)
103 %ssub = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
117 %usub = tail call { i8, i1 } @llvm.usub.with.overflow.i8(i8 %a, i8 %b
[all...] |
| /external/qemu/distrib/sdl-1.2.15/src/events/ |
| SDL_events.c | 46 int tail; member in struct:__anon13096
222 SDL_EventQ.tail = 0;
267 int tail, added; local
269 tail = (SDL_EventQ.tail+1)%MAXEVENTS;
270 if ( tail == SDL_EventQ.head ) {
274 SDL_EventQ.event[SDL_EventQ.tail] = *event;
279 SDL_EventQ.event[SDL_EventQ.tail].syswm.msg =
283 SDL_EventQ.tail = tail;
[all...] |
| /frameworks/rs/driver/runtime/arch/ |
| asimd.ll | 109 %1 = tail call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %value, <4 x float> %high) nounwind readnone
110 %2 = tail call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %1, <4 x float> %low) nounwind readnone
115 %_high = tail call <4 x float> @smear_4f(float %high) nounwind readnone
116 %_low = tail call <4 x float> @smear_4f(float %low) nounwind readnone
117 %out = tail call <4 x float> @_Z5clampDv4_fS_S_(<4 x float> %value, <4 x float> %_low, <4 x float> %_high) nounwind readonly
125 %a = tail call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %_value, <4 x float> %_high) nounwind readnone
126 %b = tail call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %a, <4 x float> %_low) nounwind readnone
133 %_high = tail call <4 x float> @smear_4f(float %high) nounwind readnone
134 %_low = tail call <4 x float> @smear_4f(float %low) nounwind readnone
135 %a = tail call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %_value, <4 x float> %_high) nounwind r (…)
[all...] |
| /external/chromium_org/components/autofill/core/browser/ |
| form_field_unittest.cc | 47 EXPECT_FALSE(FormField::Match(&field, ASCIIToUTF16("^tail"),
54 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("tail$"),
61 EXPECT_FALSE(FormField::Match(&field, ASCIIToUTF16("^tail$"),
81 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("head.*tail"),
84 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("head.*tail"),
87 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("head.*tail"),
90 EXPECT_FALSE(FormField::Match(&field, ASCIIToUTF16("head.+tail"),
93 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("head.+tail"),
96 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("head.+tail"),
103 EXPECT_TRUE(FormField::Match(&field, ASCIIToUTF16("tail|other")
[all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/libyasm/tests/ |
| splitpath_test.c | 34 size_t (*splitpath) (const char *path, const char **tail);
42 /* correct tail returned */
43 const char *tail; member in struct:Test_Entry
106 const char *tail; local
114 headlen = test->splitpath(test->input, &tail);
123 if (strcmp(tail, test->tail) != 0) {
125 "splitpath_%s(\"%s\") bad tail: expected \"%s\", got \"%s\"!",
126 funcname, test->input, test->tail, tail);
[all...] |
