| /external/qemu/distrib/jpeg-6b/ |
| jidctintelsse.c | 116 __m128i t0, t1, t2, t3, t4, t5, t6, t7; local
193 t7 = _mm_adds_epi16(tp765, tm765);\
194 t7 = _mm_adds_epi16(t7, *( __m128i*)M128_one_corr);\
232 temp = _mm_adds_epi16(t0, t7); /*y0*/ \
263 temp2 = _mm_subs_epi16(t0, t7);\
|
| /external/valgrind/main/none/tests/mips32/ |
| mips32_dspr2.stdout.exp | 5 absq_s.qb $t6, $t7 :: rd 0x73467f44 rt 0x734680bc DSPControl 0x100000
13 absq_s.qb $t6, $t7 :: rd 0x0773437b rt 0xf973437b DSPControl 0x0
21 absq_s.qb $t6, $t7 :: rd 0x0000027a rt 0x00000286 DSPControl 0x0
29 absq_s.qb $t6, $t7 :: rd 0x06415506 rt 0xfabfabfa DSPControl 0x0
37 absq_s.qb $t6, $t7 :: rd 0x7b114219 rt 0x7b11bee7 DSPControl 0x0
46 addqh.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x3d55e6ba
53 addqh.ph $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x74cd8000
61 addqh.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff1226
69 addqh.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xf352d352
77 addqh.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xe82f262
[all...] |
| /external/clang/test/Sema/ |
| array-init.c | 209 union {char a; int b;} t7[] = {1, 2, 3}; variable in typeref:union:__anon2763
210 int t8[sizeof t7 == (3*sizeof(int)) ? 1 : -1];
|
| unused-expr.c | 99 int t7 __attribute__ ((warn_unused_result)); // expected-warning {{'warn_unused_result' attribute only applies to functions}}
|
| /external/clang/test/CXX/except/except.spec/ |
| p5-pointers.cpp | 65 void (*(*t7)())() throw(B1) = &s8; // valid
|
| /external/clang/test/CodeGen/ |
| complex.c | 91 double t7(double _Complex c) { function
|
| asm.c | 40 void t7(int a) { function
41 __asm__ volatile("T7 NAMED: %[input]" : "+r"(a): [input] "i" (4));
42 // CHECK: @t7(i32
43 // CHECK: T7 NAMED: $1
|
| libcalls-fno-builtin.c | 55 char *t7(char *x) { return strncat(x, "", 1); } function
56 // CHECK: t7
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.s | 131 t7 RN 7 label
237 MOV t7,#0
243 SEL t1, t7, filt ;// aqflg = filt && (aq<beta)
297 SEL aqflg, t7, filt ;// aqflg = filt && (aq<beta)
|
| /external/llvm/test/MC/Mips/ |
| mips64-register-names-n32-n64.s | 29 daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00]
48 # [*] - t0-t3 are aliases of t4-t7 for compatibility with both the original
49 # ABI documentation (using t4-t7) and GNU As (using t0-t3)
|
| mips_directives.s | 49 .set STORE_MASK,$t7
|
| /external/valgrind/main/VEX/priv/ |
| guest_mips_toIR.c | 2374 IRTemp t0, t1 = 0, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, local
11686 IRTemp t0, t1 = 0, t2, t3, t4, t5, t6, t7; local
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips.cc | 139 __ li(t7, 0x80000000);
158 __ subu(v1, t7, t0); // 0x7ffffffc
169 __ slt(v0, t7, t3);
172 __ sltu(v0, t7, t3);
205 // Uses t0-t7 as set above.
211 __ Clz(v1, t7); // 0
217 __ Movz(a0, t6, t7); // a0 not updated (t7 is NOT 0).
666 __ Ror(t7, t0, 0x001c);
675 __ sw(t7, MemOperand(a0, OFFSET_OF(T, result_rotr_28)) )
[all...] |
| /external/clang/test/CodeGenCXX/ |
| new.cpp | 83 void t7() { function
|
| /external/clang/test/Misc/ |
| integer-literal-printing.cpp | 76 struct Type7<wcharTy::c, "7"> t7; // expected-error{{value of type 'const char [2]' is not implicitly convertible to 'typename Type7Helper<(wcharTy)L'\x00'>::Ty' (aka 'wcharTy')}} local
|
| /external/clang/test/SemaCXX/ |
| vararg-non-pod.cpp | 116 void t7(int n, ...) { function
|
| abstract.cpp | 75 void t7(Abstract a);
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 12 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 27 msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/src/mips/ |
| codegen-mips.cc | 196 __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
206 __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
215 __ lw(t7, MemOperand(a1, 15, loadstore_chunk));
225 __ sw(t7, MemOperand(a0, 15, loadstore_chunk));
246 __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
255 __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
360 __ lwr(t7, MemOperand(a1, 7, loadstore_chunk));
375 __ lwl(t7,
395 __ lwl(t7, MemOperand(a1, 7, loadstore_chunk));
410 __ lwr(t7,
[all...] |
| builtins-mips.cc | 441 // Use t7 to hold undefined, which is used in several places below.
442 __ LoadRoot(t7, Heap::kUndefinedValueRootIndex);
462 __ InitializeFieldsWithFiller(t5, a0, t7);
464 __ LoadRoot(t7, Heap::kOnePointerFillerMapRootIndex);
474 __ InitializeFieldsWithFiller(t5, a0, t7);
478 __ LoadRoot(t7, Heap::kAllocationMementoMapRootIndex);
480 __ sw(t7, MemOperand(t5));
483 __ lw(t7, MemOperand(sp, 2 * kPointerSize));
485 __ sw(t7, MemOperand(t5));
490 __ InitializeFieldsWithFiller(t5, a0, t7);
[all...] |
| /external/linux-tools-perf/perf-3.12.0/arch/ia64/lib/ |
| memcpy_mck.S | 49 #define t7 t3 // alias! define
53 #define t11 t7 // alias!
231 EK(.ex_handler, (p[D]) ld8 t7 = [src1], 3*8)
238 EK(.ex_handler, (p[D]) st8 [dst1] = t7, 3*8)
445 EX(.ex_handler_short, (p10) ld1 t7=[src0],2)
449 EX(.ex_handler_short, (p10) st1 [dst0]=t7,2)
485 EK(.ex_handler_short, (p12) ld1 t7=[src0],2)
492 EK(.ex_handler_short, (p12) st1 [dst0] = t7)
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memset.S | 27 #define FILLPTRG t7
137 LONG_SRL t7, t0, 1
|
| /external/openssl/crypto/bn/asm/ |
| ppc64-mont.pl | 122 $t7="r31";
267 mulld $t7,$a0,$t3 ; ap[0]*bp[0]
271 mulld $t7,$t7,$n0 ; tp[0]*n0
287 extrdi $t4,$t7,16,48
288 extrdi $t5,$t7,16,32
289 extrdi $t6,$t7,16,16
290 extrdi $t7,$t7,16,0
294 std $t7,`$FRAME+56`($sp
[all...] |
| /external/llvm/include/llvm/Support/ |
| AlignOf.h | 173 typename T5 = char, typename T6 = char, typename T7 = char,
176 T1 t1; T2 t2; T3 t3; T4 t4; T5 t5; T6 t6; T7 t7; T8 t8; T9 t9; T10 t10; member in class:llvm::detail::AlignerImpl
183 typename T5 = char, typename T6 = char, typename T7 = char,
187 arr5[sizeof(T5)], arr6[sizeof(T6)], arr7[sizeof(T7)], arr8[sizeof(T8)],
201 typename T5 = char, typename T6 = char, typename T7 = char,
205 T6, T7, T8, T9, T10> >::Alignment,
207 T6, T7, T8, T9, T10>)> {
|
