| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 49 unsigned DestReg, unsigned SrcReg,
61 unsigned DestReg, int FrameIndex,
|
| MipsFastISel.cpp | 326 unsigned DestReg = createResultReg(RC);
328 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
329 return DestReg;
332 unsigned DestReg = createResultReg(RC);
336 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
337 return DestReg;
347 unsigned DestReg = createResultReg(RC);
353 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
355 return DestReg;
|
| Mips16InstrInfo.h | 48 unsigned DestReg, unsigned SrcReg,
60 unsigned DestReg, int FrameIndex,
|
| Mips16InstrInfo.cpp | 66 unsigned DestReg, unsigned SrcReg,
70 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
73 else if (Mips::GPR32RegClass.contains(DestReg) &&
77 (Mips::CPU16RegsRegClass.contains(DestReg)))
81 (Mips::CPU16RegsRegClass.contains(DestReg)))
89 if (DestReg)
90 MIB.addReg(DestReg, RegState::Define);
115 unsigned DestReg, int FI, const TargetRegisterClass *RC,
125 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 67 unsigned DestReg, int FrameIdx,
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
93 unsigned DestReg, unsigned SrcReg,
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
121 unsigned DestReg = MI->getOperand(0).getReg();
123 return Hexagon::IntRegsRegClass.contains(DestReg) &&
131 unsigned DestReg = MI->getOperand(0).getReg();
134 return Hexagon::IntRegsRegClass.contains(DestReg) &&
149 unsigned DestReg = MI->getOperand(0).getReg();
150 return Hexagon::IntRegsRegClass.contains(DestReg);
[all...] |
| HexagonInstrInfo.cpp | 418 unsigned DestReg, unsigned SrcReg,
420 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
421 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
424 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
425 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
428 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
431 DestReg).addReg(SrcReg).addReg(SrcReg);
434 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
437 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
439 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
[all...] |
| HexagonInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg,
96 unsigned DestReg, int FrameIndex,
100 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 120 unsigned DestReg = MI->getOperand(0).getReg();
122 bool DestIsHigh = isHighReg(DestReg);
128 DestReg, SrcReg, SystemZ::LR, 32,
131 MI->getOperand(1).setReg(DestReg);
158 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
164 DebugLoc DL, unsigned DestReg,
168 bool DestIsHigh = isHighReg(DestReg);
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
[all...] |
| SystemZInstrInfo.h | 129 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
170 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
179 unsigned DestReg, int FrameIdx,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 590 unsigned DestReg = MI->getOperand(0).getReg();
593 << TRI->getName(DestReg) << " at " << *MI);
595 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
596 ActiveChains[DestReg] = G.get();
603 unsigned DestReg = MI->getOperand(0).getReg();
608 if (DestReg != AccumReg)
623 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg));
625 if (DestReg != AccumReg) {
626 ActiveChains[DestReg] = ActiveChains[AccumReg];
638 << TRI->getName(DestReg) << "\n")
[all...] |
| AArch64InstrInfo.h | 104 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
108 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
118 MachineBasicBlock::iterator MBBI, unsigned DestReg,
165 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
170 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 343 unsigned DestReg, unsigned SrcReg,
345 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
360 if (DestReg == XCore::SP && GRSrc) {
394 unsigned DestReg, int FrameIndex,
408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 626 unsigned DestReg,
684 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
691 unsigned DestReg, unsigned SrcReg,
696 if (PPC::F8RCRegClass.contains(DestReg) &&
699 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
704 DestReg = SuperReg;
705 } else if (PPC::VRRCRegClass.contains(DestReg) &&
708 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
713 DestReg = SuperReg;
715 PPC::VSLRCRegClass.contains(DestReg)) {
[all...] |
| PPCInstrInfo.h | 77 unsigned DestReg, int FrameIdx,
151 unsigned DestReg, unsigned SrcReg,
162 unsigned DestReg, int FrameIndex,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg,
54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
63 .addReg(DestReg, RegState::Define | RegState::Implicit);
68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
|
| AMDGPUInstrInfo.h | 75 unsigned DestReg, unsigned SrcReg,
85 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 108 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
119 unsigned DestReg, int FrameIndex,
126 unsigned DestReg, unsigned SubIdx,
398 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
402 unsigned DestReg, unsigned BaseReg, int NumBytes,
408 unsigned DestReg, unsigned BaseReg, int NumBytes,
413 unsigned DestReg, unsigned BaseReg,
|
| ARMBaseInstrInfo.cpp | 664 unsigned DestReg, unsigned SrcReg,
666 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
670 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
675 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
685 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
687 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
705 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
709 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
714 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg,
54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
63 .addReg(DestReg, RegState::Define | RegState::Implicit);
68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
|
| AMDGPUInstrInfo.h | 75 unsigned DestReg, unsigned SrcReg,
85 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.h | 79 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
|
| SIInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg,
78 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 206 unsigned DestReg, unsigned SubIdx,
266 unsigned DestReg, unsigned SrcReg,
283 unsigned DestReg, int FrameIndex,
287 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 190 unsigned DestReg = MI.getOperand(0).getReg();
191 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
192 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
|
