/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 412 unsigned DstReg, 497 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { 501 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { 505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { 508 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { 540 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( 590 unsigned &SrcReg, unsigned &DstReg, 603 DstReg = MI.getOperand(0).getReg(); 1001 unsigned DstReg = MI->getOperand(0).getReg(); 1002 return (AArch64::GPR32RegClass.contains(DstReg) || [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 299 unsigned DstReg = MI->getOperand(0).getReg(); 302 if (DstReg != SrcReg) 303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 311 if (DstReg != SrcReg) 312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 320 if (DstReg != SrcReg) 321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) [all...] |
/external/llvm/lib/Target/R600/ |
R600OptimizeVectorRegisters.cpp | 190 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 196 DstReg) 210 SrcVec = DstReg;
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SIInstrInfo.h | 98 unsigned DstReg, unsigned SrcReg) const override;
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R600InstrInfo.cpp | [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_program.c | 176 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
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radeon_program_print.c | 300 rc_print_dst_register(f, inst->U.I.DstReg); 332 if (inst->U.I.DstReg.Pred == RC_PRED_SET) { 334 } else if (inst->U.I.DstReg.Pred == RC_PRED_INV) {
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
AMDGPUInstrInfo.cpp | 37 unsigned &SrcReg, unsigned &DstReg,
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R600InstrInfo.cpp | 79 unsigned DstReg, int64_t Imm) const 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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/external/chromium_org/third_party/mesa/src/src/mesa/main/ |
atifragshader.h | 56 struct atifragshader_dst_register DstReg[2];
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/external/chromium_org/third_party/mesa/src/src/mesa/swrast/ |
s_atifragshader.c | 326 GLint dstreg; local 539 dstreg = inst->DstReg[optype].Index; 540 dstp = machine->Registers[dstreg - GL_REG_0_ATI]; 544 write_dst_addr(optype, inst->DstReg[optype].dstMod, 545 inst->DstReg[optype].dstMask, dst[optype], 548 write_dst_addr(1, inst->DstReg[0].dstMod, 0, dst[1], dstp);
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_program.c | 176 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
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radeon_program_print.c | 300 rc_print_dst_register(f, inst->U.I.DstReg); 332 if (inst->U.I.DstReg.Pred == RC_PRED_SET) { 334 } else if (inst->U.I.DstReg.Pred == RC_PRED_INV) {
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUInstrInfo.cpp | 37 unsigned &SrcReg, unsigned &DstReg,
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R600InstrInfo.cpp | 79 unsigned DstReg, int64_t Imm) const 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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/external/mesa3d/src/mesa/main/ |
atifragshader.h | 56 struct atifragshader_dst_register DstReg[2];
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/external/mesa3d/src/mesa/swrast/ |
s_atifragshader.c | 326 GLint dstreg; local 539 dstreg = inst->DstReg[optype].Index; 540 dstp = machine->Registers[dstreg - GL_REG_0_ATI]; 544 write_dst_addr(optype, inst->DstReg[optype].dstMod, 545 inst->DstReg[optype].dstMask, dst[optype], 548 write_dst_addr(1, inst->DstReg[0].dstMod, 0, dst[1], dstp);
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/external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/ |
st_cb_drawpixels.c | 88 inst[0].DstReg.File == PROGRAM_OUTPUT && 89 inst[0].DstReg.Index == FRAG_RESULT_COLOR && 90 inst[0].DstReg.WriteMask == WRITEMASK_XYZW && 234 p->Instructions[ic].DstReg.File = PROGRAM_OUTPUT; 235 p->Instructions[ic].DstReg.Index = FRAG_RESULT_DEPTH; 236 p->Instructions[ic].DstReg.WriteMask = WRITEMASK_Z; 244 p->Instructions[ic].DstReg.File = PROGRAM_OUTPUT; 245 p->Instructions[ic].DstReg.Index = FRAG_RESULT_COLOR; 254 p->Instructions[ic].DstReg.File = PROGRAM_OUTPUT; 255 p->Instructions[ic].DstReg.Index = FRAG_RESULT_STENCIL [all...] |
/external/mesa3d/src/mesa/state_tracker/ |
st_cb_drawpixels.c | 88 inst[0].DstReg.File == PROGRAM_OUTPUT && 89 inst[0].DstReg.Index == FRAG_RESULT_COLOR && 90 inst[0].DstReg.WriteMask == WRITEMASK_XYZW && 234 p->Instructions[ic].DstReg.File = PROGRAM_OUTPUT; 235 p->Instructions[ic].DstReg.Index = FRAG_RESULT_DEPTH; 236 p->Instructions[ic].DstReg.WriteMask = WRITEMASK_Z; 244 p->Instructions[ic].DstReg.File = PROGRAM_OUTPUT; 245 p->Instructions[ic].DstReg.Index = FRAG_RESULT_COLOR; 254 p->Instructions[ic].DstReg.File = PROGRAM_OUTPUT; 255 p->Instructions[ic].DstReg.Index = FRAG_RESULT_STENCIL [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 184 unsigned &SrcReg, unsigned &DstReg, 261 unsigned DstReg,
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/external/llvm/lib/Target/Mips/ |
MipsSEISelDAGToDAG.cpp | 87 unsigned DstReg = 0, ZeroReg = 0; 93 DstReg = MI.getOperand(0).getReg(); 98 DstReg = MI.getOperand(0).getReg(); 102 if (!DstReg) 106 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | 116 unsigned &SrcReg, unsigned &DstReg, 438 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 449 /// @param DstReg Virtual register to be defined by select instruction. 455 unsigned DstReg, [all...] |
/external/llvm/lib/Target/ARM/ |
ARMAsmPrinter.cpp | [all...] |
MLxExpansionPass.cpp | 275 unsigned DstReg = MI->getOperand(0).getReg(); 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
prog_instruction.h | 342 struct prog_dst_register DstReg;
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