/frameworks/compile/slang/ |
slang_rs_reflection_cpp.h | 117 void genGetterAndSetter(const RSExportVectorType *EVT, const RSExportVar* EV);
|
slang_rs_export_type.h | 410 // @EVT was normalized by calling RSExportType::NormalizeType() before 413 const clang::ExtVectorType *EVT, 420 static llvm::StringRef GetTypeName(const clang::ExtVectorType *EVT);
|
/external/llvm/lib/Target/AArch64/ |
AArch64ISelDAGToDAG.cpp | 345 EVT SrcVT; 362 EVT SrcVT = N.getOperand(0).getValueType(); 881 EVT VT = N->getValueType(0); [all...] |
AArch64TargetTransformInfo.cpp | 300 EVT SrcTy = TLI->getValueType(Src); 301 EVT DstTy = TLI->getValueType(Dst); 459 EVT SelCondTy = TLI->getValueType(CondTy); 460 EVT SelValTy = TLI->getValueType(ValTy);
|
AArch64FastISel.cpp | 254 EVT DestEVT = TLI.getValueType(GV->getType(), true); 289 EVT CEVT = TLI.getValueType(C->getType(), true); 415 EVT evt = TLI.getValueType(Ty, true); local 418 if (evt == MVT::Other || !evt.isSimple()) 420 VT = evt.getSimpleVT(); 883 EVT SrcEVT = TLI.getValueType(Ty, true); [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | 81 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT); 83 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, MachineMemOperand *MMO, 86 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM, 88 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, 92 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 149 bool isScalarFPTypeInSSEReg(EVT VT) const { 337 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true); local 338 if (evt == MVT::Other || !evt.isSimple() [all...] |
X86ISelLowering.cpp | 73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, 81 EVT VT = Vec.getValueType(); 82 EVT ElVT = VT.getVectorElementType(); 84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 140 EVT VT = Vec.getValueType(); 141 EVT ElVT = VT.getVectorElementType(); 142 EVT ResultVT = Result.getValueType(); 180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | 264 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1); 265 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1); 266 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1); 267 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1); 270 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 271 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 272 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonInstrInfo.h | 28 struct EVT; 159 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
|
HexagonISelLowering.cpp | 615 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, 659 EVT VT; 872 EVT RegVT = VA.getLocVT(); [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.h | 100 bool isZExtFree(SDValue Val, EVT VT2) const override; 104 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
|
XCoreISelLowering.cpp | 187 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 191 EVT VT1 = Val.getValueType(); 333 EVT PtrVT = Op.getValueType(); 428 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 506 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 759 EVT VT = Node->getValueType(0); // not an aggregate 762 EVT PtrVT = VAListPtr.getValueType(); [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600ISelLowering.cpp | 277 EVT VT = Op.getValueType(); 357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, 377 EVT VT = Op.getValueType(); 390 EVT VT = Op.getValueType(); 401 EVT CompareVT = LHS.getValueType();
|
/external/mesa3d/src/gallium/drivers/radeon/ |
R600ISelLowering.cpp | 277 EVT VT = Op.getValueType(); 357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, 377 EVT VT = Op.getValueType(); 390 EVT VT = Op.getValueType(); 401 EVT CompareVT = LHS.getValueType();
|
/external/llvm/lib/Target/R600/ |
R600ISelLowering.cpp | 625 EVT VT = Op.getValueType(); 847 EVT VT = Op.getValueType(); 856 EVT VT = Op.getValueType(); 865 EVT VT = Op.getValueType(); 874 EVT VT = Op.getValueType(); 890 EVT VT = Op.getValueType(); 891 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 454 EVT RegVT = VA.getLocVT(); 500 << EVT(VA.getLocVT()).getEVTString() 742 EVT VT = Op.getValueType(); [all...] |
MSP430ISelDAGToDAG.cpp | 256 EVT VT = N.getValueType(); 309 EVT VT = LD->getMemoryVT();
|
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 64 static bool is32Bit(EVT VT) { 312 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 318 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { 337 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 342 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, 376 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const { 690 EVT LocVT = VA.getLocVT(); 729 EVT PtrVT = getPointerTy() [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelDAGToDAG.h | 38 EVT Ty, bool HasLo, bool HasHi);
|
MipsFastISel.cpp | 120 EVT evt = TLI.getValueType(Ty, true); local 122 if (evt == MVT::Other || !evt.isSimple()) 124 VT = evt.getSimpleVT(); 197 EVT CEVT = TLI.getValueType(C->getType(), true);
|
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |
PPCFastISel.cpp | 256 EVT Evt = TLI.getValueType(Ty, true); 259 if (Evt == MVT::Other || !Evt.isSimple()) return false; 260 VT = Evt.getSimpleVT(); 736 EVT SrcEVT = TLI.getValueType(Ty, true); 830 EVT SrcVT = TLI.getValueType(Src->getType(), true); 831 EVT DestVT = TLI.getValueType(I->getType(), true); 848 EVT SrcVT = TLI.getValueType(Src->getType(), true); 849 EVT DestVT = TLI.getValueType(I->getType(), true) [all...] |
/external/llvm/lib/CodeGen/ |
Analysis.cpp | 76 SmallVectorImpl<EVT> &ValueVTs, 102 // Base case: we can get an EVT for this LLVM IR type. 209 TLI.isTypeLegal(EVT::getEVT(T1)) && TLI.isTypeLegal(EVT::getEVT(T2)));
|
BasicTargetTransformInfo.cpp | 175 EVT T = getTLI()->getValueType(Ty); 196 EVT VT = TLI->getValueType(Ty); 513 EVT MemVT = getTLI()->getValueType(Src, true);
|
/external/llvm/lib/Target/NVPTX/ |
NVPTXGenericToNVVM.cpp | 169 EVT ExtendedGVType = EVT::getEVT(GVType->getElementType(), true);
|