| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 98 case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break;
530 // Do a non-extending load followed by FP_EXTEND.
[all...] |
| LegalizeVectorOps.cpp | 199 if (Op.getOpcode() == ISD::LOAD) {
457 // load each element by advancing pointer, which could only address bytes.
458 // Instead, we load all significant words, mask bits off, and concatenate
487 LoadBytes >>= 1; // Reduce the load size by half.
539 default: llvm_unreachable("Unknown extended-load op!");
[all...] |
| LegalizeVectorTypes.cpp | 60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
214 assert(N->isUnindexed() && "Indexed vector load?");
574 case ISD::LOAD:
811 // Load the Lo part from the stack slot.
821 // Load the Hi part from the stack slot.
[all...] |
| LegalizeIntegerTypes.cpp | 68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
444 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
758 // Handle endianness of the load.
[all...] |
| SelectionDAG.cpp | 478 case ISD::LOAD: {
624 // If the root changed (e.g. it was a dead load, update the root).
[all...] |
| LegalizeDAG.cpp | 251 /// a load from the constant pool.
258 // target can do an extending load from float to double, we put it into
261 // an FP extending load is the same cost as a normal load (such as on the x87
355 // Load one integer register's worth from the stack slot.
356 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
360 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
372 // machines this requires an extending load from the stack slot to ensure
377 // Load from the stack slot
[all...] |
| /prebuilts/tools/common/m2/repository/xom/xom/1.0/ |
| xom-1.0.jar | |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 47 Align(cl::desc("Load/store alignment support"),
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
483 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
484 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
489 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
490 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 424 // If it is double-word aligned, just load.
430 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
433 InVals.push_back(Load);
464 SDValue Load ;
466 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
475 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
478 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
480 InVals.push_back(Load);
814 // Load the low part
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 727 // Default all indexed load / store to expand.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 313 if (N.getOpcode() != ISD::LOAD)
316 // If N is a load, do additional profitability checks.
355 // a load.
370 /// load's chain operand and move load below the call's chain operand.
371 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
375 if (Chain.getNode() == Load.getNode())
376 Ops.push_back(Load.getOperand(0));
381 if (Chain.getOperand(i).getNode() == Load.getNode())
382 Ops.push_back(Load.getOperand(0))
[all...] |
| /external/chromium_org/v8/src/ |
| hydrogen-instructions.h | 213 enum PropertyAccessType { LOAD, STORE };
504 // values are marked with kUint32 flag. If arithmetic shift or a load from
[all...] |
| hydrogen.h | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_tgsi.cpp | 546 NV50_IR_OPCODE_CASE(LOAD, TXF);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 173 /// Reg in an asm, because the load or store opcode would have to change.
224 // 1. This (trivially) reduces the load on the register allocator, by not
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_tgsi.cpp | 546 NV50_IR_OPCODE_CASE(LOAD, TXF);
[all...] |
| /external/chromium_org/chrome/renderer/resources/ |
| offline.js | 203 LOAD: 'load'
234 * Load and cache the image assets from the page.
250 * Load and decode base 64 encoded sounds.
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 224 // Load extented operations for i1 types must be promoted
229 // MIPS doesn't have extending float->double load/store
266 setOperationAction(ISD::LOAD, MVT::i64, Custom);
563 // load $reg, x
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 276 // a load-and-extend of a f80 constant (in cases where the constant
299 // We want to use MVC in preference to even a single load/store pair.
338 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
726 // Create the SelectionDAG nodes corresponding to a load
[all...] |
| /prebuilts/tools/common/m2/repository/xalan/xalan/2.6.0/ |
| xalan-2.6.0.jar | |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 92 setOperationAction(ISD::LOAD, VT, Promote);
93 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
585 // ARM does not have f32 extending load.
588 // ARM does not have i1 sign extending load.
591 // ARM supports all 4 flavors of integer indexed load / store.
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 130 case ISD::LOAD:
[all...] |
| /frameworks/compile/mclinker/lib/Target/ |
| GNULDBackend.cpp | [all...] |
| /build/tools/droiddoc/templates-ds/assets/js/ |
| docs.js | 14 /****** ON LOAD SET UP STUFF *********/
430 $(this).get(0).load(); // in case the video isn't seekable
600 Loading this in the head was slowing page load time */
[all...] |
