| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 38 const MachineBasicBlock &MBB = *MI->getParent();
39 const MachineFunction *MF = MBB.getParent();
92 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator I = MBB.end();
99 if (I == MBB.begin())
103 if (I == MBB.begin())
115 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
139 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
151 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
225 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
[all...] |
| AArch64RegisterInfo.cpp | 285 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
289 MachineBasicBlock::iterator Ins = MBB->begin();
291 if (Ins != MBB->end())
295 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
296 const MachineFunction &MF = *MBB->getParent();
300 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
326 MachineBasicBlock &MBB = *MI.getParent();
327 MachineFunction &MF = *MBB.getParent();
359 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 67 const MachineBasicBlock *MBB = MI->getParent();
70 while (I != MBB->end() && I->isInsideBundle()) {
|
| SIInstrInfo.cpp | 37 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| AMDGPUInstrInfo.h | 45 MachineBasicBlock &MBB) const;
73 virtual void copyPhysReg(MachineBasicBlock &MBB,
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
83 void loadRegFromStackSlot(MachineBasicBlock &MBB,
114 void insertNoop(MachineBasicBlock &MBB,
|
| /external/llvm/lib/CodeGen/ |
| SlotIndexes.cpp | 45 // Iterate over all MBBs, and within each MBB all MIs, keeping the MI
59 "Index -> MBB mapping non-empty at initial numbering?");
61 "MBB -> Index mapping non-empty at initial numbering?");
74 MachineBasicBlock *mbb = &*mbbItr; local
76 // Insert an index for the MBB start.
79 for (MachineBasicBlock::iterator miItr = mbb->begin(), miEnd = mbb->end();
96 MBBRanges[mbb->getNumber()].first = blockStartIndex;
97 MBBRanges[mbb->getNumber()].second = SlotIndex(&indexList.back(),
99 idx2MBBMap.push_back(IdxMBBPair(blockStartIndex, mbb));
[all...] |
| TailDuplication.cpp | 119 bool TailDuplicateAndUpdate(MachineBasicBlock *MBB,
123 void RemoveDeadBlock(MachineBasicBlock *MBB);
163 MachineBasicBlock *MBB = I;
164 SmallSetVector<MachineBasicBlock*, 8> Preds(MBB->pred_begin(),
165 MBB->pred_end());
166 MachineBasicBlock::iterator MI = MBB->begin();
167 while (MI != MBB->end()) {
182 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
192 dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber()
199 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI
[all...] |
| MachineCopyPropagation.cpp | 55 bool CopyPropagateBlock(MachineBasicBlock &MBB);
88 const MachineBasicBlock *MBB = CopyMI->getParent();
89 if (MI->getParent() != MBB)
92 MachineBasicBlock::const_iterator E = MBB->end();
137 bool MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
143 DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n");
146 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ) {
314 // If MBB doesn't have successors, delete the copies whose defs are not used.
315 // If MBB does have successors, then conservative assume the defs are live-ou
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600EmitClauseMarkers.cpp | 226 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) {
231 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
275 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
304 MachineBasicBlock &MBB = *BB;
305 MachineBasicBlock::iterator I = MBB.begin();
308 for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
310 I = MakeALUClause(MBB, I);
|
| SILowerI1Copies.cpp | 81 MachineBasicBlock &MBB = *BI;
83 for (I = MBB.begin(); I != MBB.end(); I = Next) {
119 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
131 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
|
| R600ExpandSpecialInstrs.cpp | 74 MachineBasicBlock &MBB = *BB;
75 MachineBasicBlock::iterator I = MBB.begin();
76 while (I != MBB.end()) {
85 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
104 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
132 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
161 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
185 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
209 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
327 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1)
[all...] |
| SIInsertWaits.cpp | 87 bool insertWait(MachineBasicBlock &MBB,
244 bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
249 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
298 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
363 MachineBasicBlock &MBB = *BI;
364 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
367 Changes |= insertWait(MBB, I, handleOperands(*I));
371 // Wait for everything at the end of the MBB
372 Changes |= insertWait(MBB, MBB.getFirstTerminator(), LastIssued)
[all...] |
| SIInstrInfo.cpp | 36 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
75 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
95 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
101 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
123 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
161 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
185 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
191 MachineFunction *MF = MBB.getParent();
194 DebugLoc DL = MBB.findDebugLoc(MI);
200 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 67 const MachineBasicBlock *MBB = MI->getParent();
70 while (I != MBB->end() && I->isInsideBundle()) {
|
| SIInstrInfo.cpp | 37 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| AMDGPUInstrInfo.h | 45 MachineBasicBlock &MBB) const;
73 virtual void copyPhysReg(MachineBasicBlock &MBB,
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
83 void loadRegFromStackSlot(MachineBasicBlock &MBB,
114 void insertNoop(MachineBasicBlock &MBB,
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 217 virtual void reMaterialize(MachineBasicBlock &MBB,
273 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
298 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
305 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
308 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
322 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
352 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
363 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
386 /// instruction latencies in the specified MBB to enable if-conversion.
391 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 52 MachineBasicBlock *MBB = MI->getParent();
53 MachineFunction &MF = *MBB->getParent();
58 MBB->insert(MI, EarlierMI);
83 MachineBasicBlock *MBB = MI->getParent();
84 MachineFunction &MF = *MBB->getParent();
158 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
162 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
241 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
[all...] |
| SystemZLongBranch.cpp | 273 MachineBasicBlock *MBB = MF->getBlockNumbered(I);
277 Block.Alignment = MBB->getAlignment();
280 MachineBasicBlock::iterator MI = MBB->begin();
281 MachineBasicBlock::iterator End = MBB->end();
349 MachineBasicBlock *MBB = MI->getParent();
351 BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
355 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
368 MachineBasicBlock *MBB = MI->getParent();
370 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
373 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 99 isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
100 if (MBB->hasAddressTaken()) {
103 return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
179 const MachineBasicBlock *MBB = MI->getParent();
183 while (MII != MBB->end() && MII->isInsideBundle()) {
|
| HexagonInstrInfo.cpp | 122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
149 MachineInstr *Term = MBB.getFirstTerminator();
150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
153 std::next(MachineFunction::iterator(&MBB));
156 RemoveBranch(MBB);
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
160 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 BuildMI(&MBB, DL,
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
169 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 570 static bool verifyCTRBranch(MachineBasicBlock *MBB,
577 if (I == MBB->begin()) {
578 Visited.insert(MBB);
584 Visited.insert(MBB);
585 if (I == MBB->end())
589 for (MachineBasicBlock::iterator IE = MBB->begin();; --I) {
597 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " (" <<
598 MBB->getFullName() << ") instruction " << *I <<
615 if (MachineFunction::iterator(MBB) == MBB->getParent()->begin())
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 71 MachineBasicBlock &MBB = MF.front();
72 MachineBasicBlock::iterator I = MBB.begin();
75 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
90 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
95 // first MBB of the function.
103 MachineBasicBlock &MBB = MF.front();
104 MachineBasicBlock::iterator I = MBB.begin();
106 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc()
[all...] |
| MipsOptimizePICCall.cpp | 74 /// \brief Visit MBB.
130 static void setCallTargetReg(MachineBasicBlock *MBB,
132 MachineFunction &MF = *MBB->getParent();
136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
189 // If this MBB has already been visited, destroy the scope for the MBB and
197 // Visit the MBB and add its children to the work list.
210 MachineBasicBlock *MBB = MBBI.getNode()->getBlock();
212 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 61 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
65 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
66 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
107 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
111 void storeRegToStackSlot(MachineBasicBlock &MBB,
117 void loadRegFromStackSlot(MachineBasicBlock &MBB,
125 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
164 const MachineBasicBlock *MBB,
167 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
176 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles
[all...] |
