| /external/llvm/lib/CodeGen/ |
| DFAPacketizer.cpp | 147 void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
151 finalizeBundle(*MBB, MIFirst, MI);
158 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
162 VLIWScheduler->startBlock(MBB);
163 VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
182 endPacket(MBB, MI);
187 if (this->ignorePseudoInstruction(MI, MBB))
208 endPacket(MBB, MI);
215 endPacket(MBB, MI);
223 endPacket(MBB, EndItr)
[all...] |
| LiveRangeCalc.cpp | 113 MachineBasicBlock *MBB = I->DomNode->getBlock();
116 std::tie(Start, End) = Indexes->getMBBRange(MBB);
124 assert(Seen.test(MBB->getNumber()));
125 LiveOut[MBB] = LiveOutPair(I->Value, (MachineDomTreeNode *)nullptr);
140 assert(KillMBB && "No MBB at Kill");
142 // Is there a def in the same MBB we can extend?
182 MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
185 if (MBB->pred_empty()) {
186 MBB->getParent()->verify();
191 !MBB->isLiveIn(PhysReg))
[all...] |
| SplitKit.h | 68 MachineBasicBlock *MBB;
170 /// isThroughBlock - Return true if CurLI is live through MBB without uses.
171 bool isThroughBlock(unsigned MBB) const { return ThroughBlocks.test(MBB); }
320 MachineBasicBlock &MBB,
327 /// getShallowDominator - Returns the least busy dominator of MBB that is
329 MachineBasicBlock *findShallowDominator(MachineBasicBlock *MBB,
379 /// enterIntvAtEnd - Enter the open interval at the end of MBB.
380 /// Use the open interval from the inserted copy to the MBB end.
382 SlotIndex enterIntvAtEnd(MachineBasicBlock &MBB);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 61 static void EmitDefCfaRegister(MachineBasicBlock &MBB,
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
71 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
81 static void EmitCfiOffset(MachineBasicBlock &MBB,
87 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
97 static void IfNeededExtSP(MachineBasicBlock &MBB,
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
121 static void IfNeededLDAWSP(MachineBasicBlock &MBB,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 106 // block MBB. IsImplicit says whether this is an explicit operand to the
109 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
111 const TargetRegisterInfo *RI = MBB.getParent()->getTarget().getRegisterInfo();
113 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
117 MBB.addLiveIn(GPR64);
122 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
129 MachineFunction &MF = *MBB.getParent();
133 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG))
[all...] |
| SystemZISelLowering.cpp | [all...] |
| SystemZShortenInst.cpp | 33 bool processBlock(MachineBasicBlock &MBB);
100 // Process all instructions in MBB. Return true if something changed.
101 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
107 for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) {
118 for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
156 for (auto &MBB : F)
157 Changed |= processBlock(MBB);
|
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 85 MachineBasicBlock &MBB);
131 MachineBasicBlock &MBB, unsigned Opc) const;
135 MachineBasicBlock &MBB) const;
160 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
161 MBB != E; ++MBB){
162 MCE.StartMachineBasicBlock(MBB);
163 for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
164 E = MBB->instr_end(); I != E;)
165 emitInstruction(*I++, *MBB);
[all...] |
| MipsLongBranch.cpp | 78 void splitMBB(MachineBasicBlock *MBB);
81 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
112 assert(false && "This instruction does not have an MBB operand.");
126 // Split MBB if it has two direct jumps/branches.
127 void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
128 ReverseIter End = MBB->rend();
129 ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
131 // Return if MBB has no branch instructions.
138 // MBB has only one branch instruction if FirstBr is not a branch
146 // Create a new MBB. Move instructions in MBB to the newly created MBB
[all...] |
| MipsSERegisterInfo.cpp | 166 MachineBasicBlock &MBB = *MI.getParent();
171 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
175 MBB.getParent()->getTarget().getInstrInfo());
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
184 MachineBasicBlock &MBB = *MI.getParent();
190 MBB.getParent()->getTarget().getInstrInfo());
191 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
|
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 57 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
88 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
92 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
110 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
115 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
123 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
130 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
139 MachineBasicBlock::iterator D = MBB.end();
142 D = findDelayInstr(MBB, MI)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 108 MachineBasicBlock* MBB = MBBb;
111 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
112 if (MII != MBB->end()) {
146 unsigned NumSuccs = MBB->succ_size();
147 MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
153 if (MBB->isLayoutSuccessor(FirstSucc)) {
156 } else if (MBB->isLayoutSuccessor(SecondSucc)) {
192 MBB->removeSuccessor(JumpAroundTarget);
193 MBB->addSuccessor(UncondTarget);
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.h | 40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
64 void copyPhysReg(MachineBasicBlock &MBB,
68 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
163 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
166 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
168 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
175 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
178 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
221 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
[all...] |
| AMDGPUInstrInfo.h | 45 MachineBasicBlock &MBB) const;
77 virtual void copyPhysReg(MachineBasicBlock &MBB,
84 void storeRegToStackSlot(MachineBasicBlock &MBB,
89 void loadRegFromStackSlot(MachineBasicBlock &MBB,
129 void insertNoop(MachineBasicBlock &MBB,
167 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
175 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
181 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 43 virtual void copyPhysReg(MachineBasicBlock &MBB,
68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
73 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
80 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
83 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 43 virtual void copyPhysReg(MachineBasicBlock &MBB,
68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
73 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
80 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
83 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 90 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
94 const MachineFunction *MF = MBB.getParent();
149 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
164 DebugLoc DL = MBB.findDebugLoc(MBBI);
172 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
207 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
209 if (MBBI == MBB.begin()) return
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 64 unsigned createDupLane(MachineBasicBlock &MBB,
70 unsigned createExtractSubreg(MachineBasicBlock &MBB,
76 unsigned createVExt(MachineBasicBlock &MBB,
81 unsigned createRegSequence(MachineBasicBlock &MBB,
86 unsigned createInsertSubreg(MachineBasicBlock &MBB,
91 unsigned createImplicitDef(MachineBasicBlock &MBB,
425 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
431 AddDefaultPred(BuildMI(MBB,
444 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
450 BuildMI(MBB,
[all...] |
| ARMOptimizeBarriersPass.cpp | 59 for (auto &MBB : MF) {
63 for (auto &MI : MBB) {
|
| Thumb1RegisterInfo.h | 39 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
52 bool saveScavengerRegister(MachineBasicBlock &MBB,
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DbgValueHistoryCalculator.cpp | 126 // \brief Returns the first instruction in @MBB which corresponds to
127 // the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
128 static const MachineInstr *getFirstEpilogueInst(const MachineBasicBlock &MBB) {
129 auto LastMI = MBB.getLastNonDebugInstr();
130 if (LastMI == MBB.end() || !LastMI->isReturn())
136 for (MachineBasicBlock::const_reverse_iterator I(std::next(LastMI)); I != MBB.rend();
142 // If all instructions have the same debug location, assume whole MBB is
144 return MBB.begin();
152 for (const auto &MBB : *MF) {
153 auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
281 const MachineInstr &Ret = MBB.back();
496 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
497 MachineBasicBlock::iterator MBBI = MBB.begin();
521 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
529 MBBI = MBB.begin();
620 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
627 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg)
[all...] |
| PPCRegisterInfo.cpp | 275 MachineBasicBlock &MBB = *MI.getParent();
277 MachineFunction &MF = *MBB.getParent();
308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
333 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
338 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
344 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
348 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
358 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineBranchProbabilityInfo.h | 60 uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) const;
68 MachineBasicBlock *getHotSucc(MachineBasicBlock *MBB) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 135 MachineBasicBlock &MBB) const = 0;
149 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
160 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
228 MachineBasicBlock &MBB,
|
