/external/chromium_org/v8/src/arm64/ |
macro-assembler-arm64-inl.h | 294 #define DEFINE_FUNCTION(FN, REGTYPE, REG, OP) \ 295 void MacroAssembler::FN(const REGTYPE REG, const MemOperand& addr) { \ 297 LoadStoreMacro(REG, addr, OP); \ 303 #define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ 304 void MacroAssembler::FN(const REGTYPE REG, const REGTYPE REG2, \ 307 LoadStorePairMacro(REG, REG2, addr, OP); \ [all...] |
macro-assembler-arm64.h | 262 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \ 263 inline void FN(const REGTYPE REG, const MemOperand& addr); 271 #define DECLARE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ 272 inline void FN(const REGTYPE REG, const REGTYPE REG2, const MemOperand& addr); 301 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1); 728 inline void TestAndBranchIfAnySet(const Register& reg, 734 inline void TestAndBranchIfAllClear(const Register& reg, [all...] |
/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
defaults.h | 438 #define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG) [all...] |
rtl.def | 51 an rtx code that can be used to represent an object (e.g, REG, MEM) 262 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 354 can change REG rtx's into MEMs during reload. */ 355 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) 358 single insn. It will be turned into a REG during register allocation 361 marked as having one operand so it can be turned into a REG. */ 370 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 371 has an unspecified effect on the high part of REG, 372 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...) [all...] |
genrtl.h | 931 gen_rtx_fmt_i00 (REG, (MODE), (ARG0)) [all...] |
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/parsers/nasm/ |
nasm-token.re | 415 RETURN(REG); 710 RETURN(REG);
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nasm-parse.c | 179 case REG: str = "register"; break; 932 uintptr_t reg = REGGROUP_val; local [all...] |
/bionic/libc/arch-x86/atom/string/ |
ssse3-memcmp-atom.S | 44 # define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off 48 # define cfi_restore(reg) .cfi_restore reg 82 #define CFI_PUSH(REG) \ 84 cfi_rel_offset (REG, 0) 86 #define CFI_POP(REG) \ 88 cfi_restore (REG) 90 #define PUSH(REG) pushl REG; CFI_PUSH (REG [all...] |
ssse3-memcpy-atom.S | 50 # define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off 54 # define cfi_restore(reg) .cfi_restore reg 86 #define CFI_PUSH(REG) \ 88 cfi_rel_offset (REG, 0) 90 #define CFI_POP(REG) \ 92 cfi_restore (REG) 94 #define PUSH(REG) pushl REG; CFI_PUSH (REG [all...] |
ssse3-strcpy-atom.S | 46 # define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off 50 # define cfi_restore(reg) .cfi_restore reg 72 # define CFI_PUSH(REG) \ 74 cfi_rel_offset (REG, 0) 76 # define CFI_POP(REG) \ 78 cfi_restore (REG) 80 # define PUSH(REG) pushl REG; CFI_PUSH (REG [all...] |
/external/chromium_org/v8/src/x64/ |
macro-assembler-x64.cc | 906 #define REG(Name) { kRegister_ ## Name ## _Code } 909 REG(rax), REG(rcx), REG(rdx), REG(rbx), REG(rbp), REG(rsi), REG(rdi), REG(r8), 910 REG(r9), REG(r10), REG(r11 926 Register reg = saved_regs[i]; local 935 XMMRegister reg = XMMRegister::from_code(i); local 936 movsd(Operand(rsp, i * kDoubleSize), reg); local 948 XMMRegister reg = XMMRegister::from_code(i); local 954 Register reg = saved_regs[i]; local 4054 XMMRegister reg = XMMRegister::FromAllocationIndex(i); local 4055 movsd(Operand(rbp, offset - ((i + 1) * kDoubleSize)), reg); local 4098 XMMRegister reg = XMMRegister::FromAllocationIndex(i); local [all...] |
/external/vixl/src/a64/ |
macro-assembler-a64.cc | 30 void MacroAssembler::B(Label* label, BranchType type, Register reg, int bit) { 31 VIXL_ASSERT((reg.Is(NoReg) || (type >= kBranchTypeFirstUsingReg)) && 39 case reg_zero: Cbz(reg, label); break; 40 case reg_not_zero: Cbnz(reg, label); break; 41 case reg_bit_clear: Tbz(reg, bit, label); break; 42 case reg_bit_set: Tbnz(reg, bit, label); break; 194 VIXL_ASSERT(operand.reg().size() <= rd.size()); 198 VIXL_ASSERT(operand.reg().Is64Bits() || 201 temps.Exclude(operand.reg()); 203 EmitExtendShift(temp, operand.reg(), operand.extend() [all...] |
macro-assembler-a64.h | 211 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \ 212 void FN(const REGTYPE REG, const MemOperand& addr); 376 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1); [all...] |
/art/compiler/dex/quick/ |
mir_to_lir.h | 208 #define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 280 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 376 void SetReg(RegStorage reg) { reg_ = reg; } 429 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 499 // CMP reg, #value 669 void SetupRegMask(ResourceMask* mask, int reg); 670 void ClearRegMask(ResourceMask* mask, int reg); 738 void Clobber(RegStorage reg); [all...] |