| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 38 const SparcRegisterInfo RI;
48 const SparcRegisterInfo &getRegisterInfo() const { return RI; }
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 26 const XCoreRegisterInfo RI;
35 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 27 RI(tm, *this),
33 return RI;
|
| AMDGPUInstrInfo.cpp | 30 : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { }
33 return RI;
242 const AMDGPURegisterInfo & RI = getRegisterInfo();
250 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
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| AMDGPUAsmPrinter.cpp | 58 const SIRegisterInfo * RI =
111 hwReg = RI->getHWRegNum(reg);
|
| /ndk/sources/host-tools/sed-4.2.1/doc/ |
| sed.x | 36 .RI :\ label
43 .RI # comment
80 .RI r\ filename
84 .RI R\ filename
95 .RI b\ label
102 .RI t\ label
111 .RI T\ label
149 .RI l\ width
164 .RI s/ regexp / replacement /
180 .RI w\ filenam
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| InlineFunction.cpp | 86 void forwardResume(ResumeInst *RI,
145 void InvokeInliningInfo::forwardResume(ResumeInst *RI,
148 BasicBlock *Src = RI->getParent();
156 InnerEHValuesPHI->addIncoming(RI->getOperand(0), Src);
157 RI->eraseFromParent();
252 if (ResumeInst *RI = dyn_cast<ResumeInst>(BB->getTerminator()))
253 Invoke.forwardResume(RI, InlinedLPads);
491 static CallInst *getPrecedingMustTailCall(ReturnInst *RI) {
492 Instruction *Prev = RI->getPrevNode();
496 if (Value *RV = RI->getReturnValue())
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 286 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
289 unsigned PC = RI.getProgramCounter();
292 if (hasDefOfPhysReg(MI, PC, RI))
300 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
564 const MCRegisterInfo &RI) const {
567 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
569 return hasImplicitDefOfPhysReg(Reg, &RI);
|
| MCRegisterInfo.h | 517 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
518 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
561 MCRegUnitIterator RI;
570 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
571 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
581 return RI.isValid()
[all...] |
| /external/llvm/lib/Analysis/ |
| RegionInfo.cpp | 56 : RegionNode(Parent, Entry, 1), RI(RInfo), DT(dt), exit(Exit) {}
88 for (Region::const_iterator RI = R->begin(), RE = R->end(); RI != RE; ++RI)
89 if ((*RI)->getEntry() == OldEntry)
90 RegionQueue.push_back(RI->get());
104 for (Region::const_iterator RI = R->begin(), RE = R->end(); RI != RE; ++RI)
105 if ((*RI)->getExit() == OldExit
[all...] |
| RegionPass.cpp | 35 RI = nullptr;
55 RI = &getAnalysis<RegionInfo>();
61 addRegionIntoQueue(*RI->getTopLevelRegion(), RQ);
149 RI->clearNodeCache();
162 RI->dump();
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 30 : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { }
33 return RI;
242 const AMDGPURegisterInfo & RI = getRegisterInfo();
250 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
|
| AMDGPUAsmPrinter.cpp | 58 const SIRegisterInfo * RI =
111 hwReg = RI->getHWRegNum(reg);
|
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 265 for (unsigned RI = 0, RE = 17; RI < RE; ++RI) {
266 if (GPRMask & (1 << RI)) {
269 OS << GPRRegisterNames[RI];
279 for (unsigned RI = 0, RE = 32; RI < RE; ++RI) {
280 if (VFPMask & (1 << RI)) {
283 OS << Prefix << RI;
[all...] |
| ARMWinEHPrinter.cpp | 159 for (unsigned RI = 0, RE = 11; RI < RE; ++RI) {
160 if (GPRMask & (1 << RI)) {
163 OS << GPRRegisterNames[RI];
167 for (unsigned RI = 0, RE = 32; RI < RE; ++RI) {
168 if (VFPMask & (1 << RI)) {
171 OS << "d" << unsigned(RI);
[all...] |
| /external/llvm/lib/CodeGen/ |
| StackProtector.cpp | 269 /// Identify if RI has a previous instruction in the "Tail Position" and return
278 static CallInst *FindPotentialTailCall(BasicBlock *BB, ReturnInst *RI,
310 returnTypeIsEligibleForTailCall(BB->getParent(), CI, RI, *TLI))
336 static bool CreatePrologue(Function *F, Module *M, ReturnInst *RI,
340 PointerType *PtrTy = Type::getInt8PtrTy(RI->getContext());
344 ConstantInt::get(Type::getInt32Ty(RI->getContext()), Offset);
381 ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator());
382 if (!RI)
388 CreatePrologue(F, M, RI, TLI, Trip, AI, StackGuardVar);
395 if (CallInst *CI = FindPotentialTailCall(BB, RI, TLI))
[all...] |
| MachineInstrBundle.cpp | 254 VirtRegInfo RI = { false, false, false };
266 RI.Reads = true;
268 RI.Tied = true;
273 RI.Writes = true;
274 else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo()))
275 RI.Tied = true;
277 return RI;
|
| GCStrategy.cpp | 383 for (GCFunctionInfo::roots_iterator RI = FI->roots_begin();
384 RI != FI->roots_end();) {
386 if (MF.getFrameInfo()->isDeadObjectIndex(RI->Num)) {
387 RI = FI->removeStackRoot(RI);
389 RI->StackOffset = TFI->getFrameIndexOffset(MF, RI->Num);
390 ++RI;
|
| InlineSpiller.cpp | 244 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
245 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
246 MachineInstr *MI = &*(RI++);
284 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
285 MachineInstr *MI = &*(RI++);
887 MIBundleOperands::VirtRegInfo RI =
[all...] |
| LiveIntervalAnalysis.cpp | 554 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
555 ++RI) {
557 if (RI->end.isBlock())
559 MachineInstr *MI = getInstructionFromIndex(RI->end);
563 // Check if any of the regunits are live beyond the end of RI. That could
577 I = RRanges.advanceTo(I, RI->end);
578 if (I == RRanges.end() || I->start >= RI->end)
580 // I is overlapping RI.
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| RegionIterator.h | 329 static NodeType *getEntryNode(RegionInfo *RI) {
330 return GraphTraits<FlatIt<Region*> >::getEntryNode(RI->getTopLevelRegion());
332 static nodes_iterator nodes_begin(RegionInfo* RI) {
333 return nodes_iterator::begin(getEntryNode(RI));
335 static nodes_iterator nodes_end(RegionInfo *RI) {
336 return nodes_iterator::end(getEntryNode(RI));
|
| RegionPass.h | 88 RegionInfo *RI;
|
| /external/llvm/tools/obj2yaml/ |
| elf2yaml.cpp | 228 for (auto RI = Obj.begin_rel(Shdr), RE = Obj.end_rel(Shdr); RI != RE;
229 ++RI) {
231 if (std::error_code EC = dumpRelocation(Shdr, &*RI, R))
248 for (auto RI = Obj.begin_rela(Shdr), RE = Obj.end_rela(Shdr); RI != RE;
249 ++RI) {
251 if (std::error_code EC = dumpRelocation(Shdr, &*RI, R))
253 R.Addend = RI->r_addend;
|
| /external/llvm/lib/Transforms/Scalar/ |
| TailRecursionElimination.cpp | 115 bool ProcessReturningBlock(ReturnInst *RI, BasicBlock *&OldEntry,
478 static bool isDynamicConstant(Value *V, CallInst *CI, ReturnInst *RI) {
500 if (BasicBlock *UniquePred = RI->getParent()->getUniquePredecessor())
503 return SI->getDefaultDest() != RI->getParent();
518 ReturnInst *RI = dyn_cast<ReturnInst>(BBI->getTerminator());
519 if (RI == nullptr || RI == IgnoreRI) continue;
525 Value *RetOp = RI->getOperand(0);
526 if (!isDynamicConstant(RetOp, CI, RI))
782 if (ReturnInst *RI = dyn_cast<ReturnInst>(BBI->getTerminator())
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 29 RI(st) { }
162 get(Opcode), RI.getSubReg(DestReg, SubIdx));
164 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
197 if (RI.hasVGPRs(RC)) {
210 } else if (RI.isSGPRClass(RC)) {
248 if (RI.hasVGPRs(RC)) {
253 } else if (RI.isSGPRClass(RC)){
328 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
352 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
377 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg()))
[all...] |
