| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 317 void SRA(int Rd, int Rt, int shft);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 818 case ISD::SRA: {
828 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
829 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
[all...] |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 297 case ISD::SRA:
[all...] |
| AArch64ISelLowering.cpp | 514 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SRA);
99 setTargetDAGCombine(ISD::SRA);
266 setOperationAction(ISD::SRA, Ty, Legal);
885 // the ISD::SRA and ISD::SHL nodes.
886 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
[all...] |
| MipsISelLowering.cpp | 621 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
630 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 586 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 296 setOperationAction(ISD::SRA, VT, Expand);
[all...] |
| /external/llvm/lib/TableGen/ |
| Record.cpp | 956 case SRA:
967 case SRA: Result = LHSv >> RHSv; break;
993 case SRA: Result = "!sra"; break;
[all...] |
| TGParser.cpp | 924 case tgtok::XSRA: Code = BinOpInit::SRA; Type = IntRecTy::get(); break;
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeSPARC_common.c | 152 #define SRA (OPC1(0x2) | OPC3(0x27))
801 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(SLJIT_R0) | IMM(31), DR(TMP_REG1)));
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 263 case ISD::SRA:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| SelectionDAG.cpp | 494 case ISD::SRA:
[all...] |
| LegalizeVectorTypes.cpp | 121 case ISD::SRA:
638 case ISD::SRA:
[all...] |
| TargetLowering.cpp | 733 case ISD::SRA:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 125 setOperationAction(ISD::SRA, VT, Custom);
554 setTargetDAGCombine(ISD::SRA);
626 setOperationAction(ISD::SRA, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 59 case ISD::SRA:
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
[all...] |
| /cts/suite/cts/deviceTests/browserbench/assets/octane/ |
| gbemu.js | [all...] |
| /external/chromium_org/v8/src/mips/ |
| simulator-mips.cc | [all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 931 enum BinaryOp { ADD, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ };
[all...] |
