| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 621 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
630 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::SRL);
267 setOperationAction(ISD::SRL, Ty, Legal);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 295 case ISD::SRL:
[all...] |
| AArch64ISelLowering.cpp | 515 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| SelectionDAGBuilder.h | 713 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
| SelectionDAGDumper.cpp | 179 case ISD::SRL: return "srl";
|
| LegalizeTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | 122 case ISD::SRL:
639 case ISD::SRL:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 586 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
| X86ISelDAGToDAG.cpp | 785 if (Shift.getOpcode() != ISD::SRL ||
799 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
800 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
810 InsertDAGNode(DAG, N, Srl);
[all...] |
| /external/chromium_org/v8/src/mips/ |
| constants-mips.h | 374 SRL = ((0 << 3) + 2),
|
| /external/chromium_org/v8/src/mips64/ |
| constants-mips64.h | 351 SRL = ((0 << 3) + 2),
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 95 SRL, SRA, SHL,
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 315 void SRL(int Rd, int Rt, int shft);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 817 case ISD::SRL:
829 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
834 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
[all...] |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 297 setOperationAction(ISD::SRL, VT, Expand);
[all...] |
| SIISelLowering.cpp | 857 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 167 #define SRL (HI(0) | LO(2))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 126 setOperationAction(ISD::SRL, VT, Custom);
553 setTargetDAGCombine(ISD::SRL);
625 setOperationAction(ISD::SRL, MVT::i64, Custom);
[all...] |
| ARMISelDAGToDAG.cpp | 337 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
341 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
343 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
373 // Look for (and (srl X, c1), c2).
374 SDValue Srl = N1.getOperand(0);
376 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
395 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32
[all...] |
| /external/llvm/lib/TableGen/ |
| Record.cpp | 957 case SRL: {
968 case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
994 case SRL: Result = "!srl"; break;
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 406 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
523 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
[all...] |
