| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 264 case ISD::SRL:
[all...] |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 495 case ISD::SRL:
[all...] |
| LegalizeFloatTypes.cpp | 201 SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit,
[all...] |
| SelectionDAGBuilder.cpp | 423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 60 case ISD::SRL:
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeSPARC_common.c | 154 #define SRL (OPC1(0x2) | OPC3(0x26))
[all...] |
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.cc | 1615 void Assembler::srl(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| simulator-mips.cc | [all...] |
| /external/chromium_org/v8/src/mips64/ |
| assembler-mips64.cc | 1679 void Assembler::srl(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| simulator-mips64.cc | [all...] |
| /cts/suite/cts/deviceTests/browserbench/assets/octane/ |
| gbemu.js | [all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 931 enum BinaryOp { ADD, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ };
[all...] |
| /external/llvm/lib/TableGen/ |
| TGParser.cpp | 925 case tgtok::XSRL: Code = BinOpInit::SRL; Type = IntRecTy::get(); break;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
