| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsSEISelLowering.cpp | [all...] |
| MipsSEISelDAGToDAG.cpp | 132 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
153 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
157 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
167 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
182 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
185 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
211 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 65 const TargetInstrInfo &TII;
75 /// tii.isTriviallyReMaterializable().
122 TII(*MF.getTarget().getInstrInfo()),
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| DFAPacketizer.h | 96 const TargetInstrInfo *TII;
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| ResourcePriorityQueue.h | 62 const TargetInstrInfo *TII;
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| /external/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 77 const TargetInstrInfo &TII) {
89 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis()))
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| DFAPacketizer.cpp | 131 TII = TM.getInstrInfo();
132 ResourceTracker = TII->CreateTargetScheduleState(&TM, nullptr);
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| OptimizePHIs.cpp | 33 const TargetInstrInfo *TII;
69 TII = Fn.getTarget().getInstrInfo();
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| SplitKit.h | 48 const TargetInstrInfo &TII;
217 const TargetInstrInfo &TII;
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| AggressiveAntiDepBreaker.h | 120 const TargetInstrInfo *TII;
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| InlineSpiller.cpp | 69 const TargetInstrInfo &TII;
154 TII(*mf.getTarget().getInstrInfo()),
254 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
258 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
622 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
744 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
803 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
806 MI->setDesc(TII.get(TargetOpcode::KILL));
[all...] |
| MachineLICM.cpp | 65 const TargetInstrInfo *TII;
328 TII = TM->getInstrInfo();
488 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
810 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
[all...] |
| StackSlotColoring.cpp | 51 const TargetInstrInfo *TII;
380 if (TII->isStackSlotCopy(I, FirstSS, SecondSS) &&
394 if (!(LoadReg = TII->isLoadFromStackSlot(I, FirstSS))) continue;
395 if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue;
425 TII = MF.getTarget().getInstrInfo();
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| PeepholeOptimizer.cpp | 108 const TargetInstrInfo *TII;
266 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
393 TII->get(TargetOpcode::COPY), NewVR)
419 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
425 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
439 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
443 if (!TII->optimizeSelect(MI))
584 TII->get(TargetOpcode::COPY), NewVR)
658 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
677 TII = TM->getInstrInfo()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 55 const ARMBaseInstrInfo *TII;
434 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
453 TII->get(TargetOpcode::COPY), Out)
469 TII->get(TargetOpcode::REG_SEQUENCE), Out)
488 TII->get(ARM::VEXTd32), Out)
504 TII->get(TargetOpcode::INSERT_SUBREG), Out)
520 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
679 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
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| Thumb2ITBlockPass.cpp | 33 const Thumb2InstrInfo *TII;
183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
258 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
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| ARMBaseInstrInfo.h | 404 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
410 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
414 int NumBytes, const TargetInstrInfo &TII,
433 const ARMBaseInstrInfo &TII);
437 const ARMBaseInstrInfo &TII);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 130 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
202 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
219 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
228 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
244 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
286 const TargetInstrInfo *TII) {
302 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
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| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 30 const AArch64InstrInfo *TII;
34 AArch64RegisterInfo(const AArch64InstrInfo *tii, const AArch64Subtarget *sti);
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| AArch64LoadStoreOptimizer.cpp | 56 const AArch64InstrInfo *TII;
312 I->getDebugLoc(), TII->get(NewOpc))
445 if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
540 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
583 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
649 TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
704 unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
805 if (TII->isLdStPairSuppressed(MI)) {
910 TII->getRegClass(MI->getDesc(), 0, TRI, *(MBB.getParent()))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 285 const TargetInstrInfo *TII = TM->getInstrInfo();
350 const MCInstrDesc &TID = TII->get(Inst.getOpcode());
352 const TargetInstrDesc &TID = TII->get(Inst.getOpcode());
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| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 83 const TargetInstrInfo *TII;
160 BuildMI(MBB, I, dl, TII->get(X86::VZEROUPPER));
253 TII = MF.getTarget().getInstrInfo();
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| X86FloatingPoint.cpp | 76 const TargetInstrInfo *TII; // Machine instruction info.
254 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
263 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
357 TII = MF.getTarget().getInstrInfo();
842 I->setDesc(TII->get(Opcode));
846 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
[all...] |
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 285 const TargetInstrInfo *TII = TM->getInstrInfo();
350 const MCInstrDesc &TID = TII->get(Inst.getOpcode());
352 const TargetInstrDesc &TID = TII->get(Inst.getOpcode());
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