| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| valid.s | 7 abs.s $f9,$f16
25 c.ngle.d $f0,$f16
56 lwc1 $f16,10225($k0)
73 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| valid.s | 7 abs.s $f9,$f16
26 c.ngle.d $f0,$f16
35 cvt.d.l $f4,$f16
107 lwc1 $f16,10225($k0)
126 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| invalid-mips64r2.s | 26 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| valid.s | 7 abs.s $f9,$f16
28 c.ngle.d $f0,$f16
37 cvt.d.l $f4,$f16
110 lwc1 $f16,10225($k0)
142 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips5-wrong-error.s | 24 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
40 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| invalid-mips1.s | 13 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/openssl/crypto/ |
| alphacpuid.pl | 49 fclr $f16
|
| /external/llvm/test/MC/ARM/ |
| directive-arch_extension-fp.s | 48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
197 vcvtb.f64.f16 d0, s0
200 vcvtb.f16.f64 s0, d0
203 vcvtt.f64.f16 d0, s0
206 vcvtt.f16.f64 s0, d0
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 7 abs.s $f9,$f16
28 c.ngle.d $f0,$f16
62 lwc1 $f16,10225($k0)
99 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 10 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 299 TESTINSNMOVE("mfc1 $s7, $f16", 64, f16, s7);
328 TESTINSNMOVEt("mtc1 $s7, $f16", 64, f16, s7);
357 TESTINSNMOVE1s("mov.s $f15, $f16", 64, f15, f16);
358 TESTINSNMOVE1s("mov.s $f16, $f17", 0, f16, f17);
385 TESTINSNMOVE1d("mov.d $f14, $f16", 48, f14, f16);
[all...] |
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 7 abs.s $f9,$f16
28 c.ngle.d $f0,$f16
39 cvt.d.l $f4,$f16
130 lwc1 $f16,10225($k0)
166 msub.s $f12,$f19,$f10,$f16
170 mthc1 $zero,$f16
175 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 7 abs.s $f9,$f16
28 c.ngle.d $f0,$f16
37 cvt.d.l $f4,$f16
111 lwc1 $f16,10225($k0)
143 mul.d $f20,$f20,$f16
|
| invalid-mips64r2.s | 30 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 7 abs.s $f9,$f16
28 c.ngle.d $f0,$f16
39 cvt.d.l $f4,$f16
116 lwc1 $f16,10225($k0)
157 mul.d $f20,$f20,$f16
|
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 764 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
771 setOperationAction(ISD::FLOG , MVT::f16, Expand);
772 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
773 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
774 setOperationAction(ISD::FEXP , MVT::f16, Expand);
775 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
776 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
778 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
779 setOperationAction(ISD::FRINT, MVT::f16, Expand)
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 121 case MVT::f16: return "f16";
192 case MVT::f16: return Type::getHalfTy(Context);
256 case Type::HalfTyID: return MVT(MVT::f16);
|
| /external/llvm/test/MC/ELF/ |
| cfi.s | 95 f16: label
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-regs.s | 55 #CHECK: .cfi_offset f16, 428
172 .cfi_offset f16,428
|
| /external/oprofile/module/ia64/ |
| IA64entry.h | 43 .spillsp f16, SW(F16)+16+(off); .spillsp f17, SW(F17)+16+(off); \
|
| oprofile_stubs.S | 114 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
|
